公开(公告)号：WO2005010892A1

公开(公告)日：2005-02-03

申请号：PCT/US2004/014797

申请日：2004-05-11

Applicant: ADVANCED MICRO DEVICES, INC. ,  TRIPSAS, Nicholas, H. ,  BUYNOSKI, Matthew ,  PANGRLE, Suzette, K. ,  OKOROANYANWU, Uzodinma ,  HUI, Angela, T. ,  LYONS, Christopher, F. ,  SUBRAMANIAN, Ramkumar ,  LOPATIN, Sergey, D. ,  NGO, Minh, Van ,  KHATHURIA, Ashok, M. ,  CHANG, Mark, S. ,  CHEUNG, Patrick, K. ,  OGLESBY, Jane, V.

Inventor： TRIPSAS, Nicholas, H. ,  BUYNOSKI, Matthew ,  PANGRLE, Suzette, K. ,  OKOROANYANWU, Uzodinma ,  HUI, Angela, T. ,  LYONS, Christopher, F. ,  SUBRAMANIAN, Ramkumar ,  LOPATIN, Sergey, D. ,  NGO, Minh, Van ,  KHATHURIA, Ashok, M. ,  CHANG, Mark, S. ,  CHEUNG, Patrick, K. ,  OGLESBY, Jane, V.

IPC: G11C13/02

CPC classification number: H01L27/285 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one dielectric layer over the copper contact, forming at least one via in the dielectric layer to expose at least a portion of the copper contact, forming a polymer material in a lower portion of the via, and forming a top electrode material layer in an upper portion of the via.

Abstract translation: 本发明的一个方面涉及在通孔中制造聚合物存储器件的方法。 该方法包括提供其上具有至少一个含金属层的半导体衬底，在含金属层中形成至少一个铜触点，在铜触点上形成至少一个电介质层，在电介质层中形成至少一个通孔 露出铜触点的至少一部分，在通孔的下部形成聚合物材料，并在通孔的上部形成顶部电极材料层。

公开(公告)号：WO2003003413A2

公开(公告)日：2003-01-09

申请号：PCT/US2002/003021

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUBRAMANIAN, Ramkumar ,  TEMPLETON, Michael, K. ,  SINGH, Bhanwar ,  RANGARAJAN, Bharath

IPC: H01L

CPC classification number: H01L21/76885 ,  H01L21/76879

Abstract: The present invention involves a method for fabricating interconnecting lines and vias. According to the invention, copper is grown within the openings in a patterned coating. The patterned coating can be a resist coating or a dielectric coating. Either type of coating can be formed over a copper seed layer, whereby the seed layer is exposed within the pattern gaps. The copper seed layer can also be provided within the pattern gaps after patterning. Copper features (18) are grown within the pattern gaps by plating. Where the patterned coating is a resist, the resist is stripped leaving the copper features (18) in the inverse pattern image. The cooper features can be coated with a diffusion barrier layer and a dielectric (19). The dielectric (19) is polished to leave the dielectric filling the spaces between copper features (18). The invention provides copper lines and vias without the need for a dielectric or metal etching step. Another benefit of the invention is that lines widths can be increased by trimming the patterned coating prior to growing the copper features (18).

Abstract translation: 本发明涉及制造互连线和通孔的方法。 根据本发明，铜在图案化涂层的开口内生长。 图案化的涂层可以是抗蚀剂涂层或介电涂层。 任何一种类型的涂层可以在铜籽晶层上形成，从而种子层在图案间隙内露出。 图案化之后也可以在图案间隙内提供铜籽晶层。 铜特征（18）通过电镀在图案间隙内生长。 在图案化涂层是抗蚀剂的地方，剥离抗蚀剂，留下反向图案图案中的铜特征（18）。 铜特征可以涂覆有扩散阻挡层和电介质（19）。 电介质（19）被抛光以留下电介质填充铜特征（18）之间的空间。 本发明提供铜线和通孔，而不需要电介质或金属蚀刻步骤。 本发明的另一个好处是通过在生长铜特征（18）之前修整图案化的涂层可以增加线宽度。

公开(公告)号：WO2002063676A2

公开(公告)日：2002-08-15

申请号：PCT/US2001/048149

申请日：2001-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： WANG, Fei ,  OKADA, Lynne, A. ,  SUBRAMANIAN, Ramkumar ,  GABRIEL, Calvin, T.

IPC: H01L21/768

CPC classification number: H01L21/76835 ,  H01L21/76808 ,  H01L23/5226 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: An interconnect structure and method of forming the same in which a diffusion barrier/etch stop layer (22) is deposited over a conductive layer (20). An organic low k dielectric material (24) is deposited over the diffusion barrier/etch stop layer (22) to form a first dielectric layer (24). The first dielectric layer (24) is etched to form a slot via (50) in the first dielectric layer (24). An inorganic low k dielectric material (30) is deposited within the slot via (50) and over the first dielectric layer (24) to form a second dielectric layer (30) over the slot via (50) and the first dielectric layer (24). The re-filled via (50) is simultaneously etched with the second dielectric layer (30) in which a trench (38) is formed. The trench (38) extends in a direction that is normal to the length of the slot via (50). The entire width of the trench (38) is directly over the via (36). The re-opened via and the trench (38) are filled with a conductive material (40). In other embodiment, the first dielectric layer (24) comprises an inorganic low k dielectric layer and the second dielectric layer (30) comprises an inorganic low k dielectric layer.

Abstract translation: 一种互连结构及其形成方法，其中在导电层（20）上沉积扩散阻挡层/蚀刻停止层（22）。 有机低k介电材料（24）沉积在扩散阻挡层/蚀刻停止层（22）上以形成第一介电层（24）。 蚀刻第一介电层（24）以在第一介电层（24）中形成槽（50）。 无机低k电介质材料（30）通过（50）并在第一介电层（24）上沉积在槽内，在槽通孔（50）和第一介电层（24）之上形成第二介电层（30） ）。 通过形成沟槽（38）的第二介电层（30）同时蚀刻再填充的通孔（50）。 沟槽（38）沿与槽通孔（50）的长度方向垂直的方向延伸。 沟槽（38）的整个宽度直接在通孔（36）的上方。 重新打开的通孔和沟槽（38）填充有导电材料（40）。 在另一实施例中，第一电介质层（24）包括无机低k电介质层，第二电介质层（30）包括无机低k电介质层。

公开(公告)号：WO2005015635A2

公开(公告)日：2005-02-17

申请号：PCT/US2004/006220

申请日：2004-03-01

Applicant: ADVANCED MICRO DEVICES, INC. ,  OGLESBY, Jane, V. ,  LYONS, Christopher, F. ,  SUBRAMANIAN, Ramkumar ,  HUI, Angela, T. ,  NGO, Minh, Van ,  PANGRLE, Suzette

Inventor： OGLESBY, Jane, V. ,  LYONS, Christopher, F. ,  SUBRAMANIAN, Ramkumar ,  HUI, Angela, T. ,  NGO, Minh, Van ,  PANGRLE, Suzette

IPC: H01L27/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0014 ,  G11C13/0016 ,  G11C2213/16 ,  G11C2213/71 ,  H01L27/285 ,  H01L51/0003 ,  H01L51/0004 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0036 ,  H01L51/0037 ,  H01L51/0038 ,  H01L51/0041 ,  H01L51/005 ,  H01L51/0053 ,  H01L51/0059 ,  H01L51/0062 ,  H01L51/0077 ,  H01L51/0078 ,  H01L51/0081 ,  H01L51/0084 ,  H01L51/0085 ,  Y10S977/843 ,  Y10S977/944

Abstract: A method of making organic memory cells (104) made of two electrodes (106, 108) with a controllably conductive media (110) between the two electrodes (106, 108) is disclosed. The controllably conductive media (110) contains an organic semiconductor layer (112) and passive layer (114). The organic semiconductor layer (112) is formed using spin-on techniques with the assistance of certain solvents.

Abstract translation: 公开了一种制造由两个电极（106,108）和两个电极（106,108）之间的可控导电介质（110）制成的有机存储单元（104）的方法。 可控导电介质（110）包含有机半导体层（112）和无源层（114）。 有机半导体层（112）使用旋涂技术在某些溶剂的帮助下形成。

公开(公告)号：WO2004031859A3

公开(公告)日：2004-04-15

申请号：PCT/US2003/028682

申请日：2003-09-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： PHAN, Khoi, A. ,  SINGH, Bhanwar ,  RANGARAJAN, Bharath ,  SUBRAMANIAN, Ramkumar

IPC: H01L21/66

Abstract: The present invention provides systems and methods that facilitate performing fabrication process. Critical parameters are valued collectively as a quality matrix, which weights respective parameters according to their importance to one or more design goals. The critical parameters are weighted by coefficients according to information such as, product design, simulation, test results, yield data, electrical data and the like. The invention then can develop a quality index which is a composite "score" of the current fabrication process. A control system can then do comparisons of the quality index with design specifications in order to determine if the current fabrication process is acceptable. If the process is unacceptable, test parameters can be modified for ongoing processes and the process can be re- worked and re-performed for completed processes. As such, respective layers of a device can be customized for different specifications and quality index depending on product designs and yields.

公开(公告)号：WO2004013907A1

公开(公告)日：2004-02-12

申请号：PCT/US2003/021108

申请日：2003-07-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUBRAMANIAN, Ramkumar ,  LYONS, Christopher, F.

IPC: H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/76813 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed are methods of dual damascene processing, involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.

Abstract translation: 公开了双镶嵌加工的方法，包括在包含单层介电材料的绝缘结构中形成多个通孔; 并且（i）在所述绝缘结构中形成多个沟槽，每个沟槽沿着一组通孔开口的基本直线定位，以及（ii）使用散射测量系统监测沟槽的形成以确定沟槽深度，并且终止 当获得所需的沟槽深度时形成沟槽。

公开(公告)号：WO2003057407A1

公开(公告)日：2003-07-17

申请号：PCT/US2002/041412

申请日：2002-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANGARAJAN, Bharath ,  AVANZINO, Steven, C. ,  SUBRAMANIAN, Ramkumar ,  SINGH, Bhanwar

IPC: B24B37/04

CPC classification number: B24B49/10 ,  B24B49/04

Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer (610) that has a metal, polysilicon, and/or dielectric layer and/or substrate and electrical resistance member(s) and/or electrical resistance entities (110) located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a electrical resistance monitoring system (630) that can read the wafer (610) electrical resistance(s) from the electrical resistance member(s) and/or electrical resistance entities and that can determine wafer stress(es) based upon the electrical resistance(s) to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer electrical resistance(s) and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer electrical resistance(s) and polishing uniformity and introduction of defects during polishing. Such relationships ips are corrlated with wafer electrical resistance(s) (e.g., wafer stress(es) as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties.

Abstract translation: 提供了表征化学机械抛光工艺的系统。 该系统包括晶片（610），其具有金属，多晶硅和/或电介质层和/或基板和电阻元件和/或电阻实体（110），其位于金属，多晶硅和/或金属上的多晶硅 和/或电介质层和/或衬底。 该系统还包括电阻监测系统（630），其可以从电阻元件和/或电阻实体读取晶片（610）的电阻，并且可以基于以下方式确定晶片应力 表征化学机械抛光工艺的电阻。 这种表征包括产生关于晶片电阻和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。 这种关系与晶片电阻和抛光均匀性以及在抛光过程中引入缺陷相关。 这种关系ips与晶片电阻（例如，与诸如抛光时间，压力，速度，浆料性质和晶片/金属层性质的参数相关的晶片应力）被折射。

公开(公告)号：WO2003002990A2

公开(公告)日：2003-01-09

申请号：PCT/US2002/002990

申请日：2002-01-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SUBRAMANIAN, Ramkumar ,  RANGARAJAN, Bharath ,  SINGH, Bhanwar ,  TEMPLETON, Michael, K.

IPC: G01N21/47

CPC classification number: H01L21/7681 ,  G01N21/4738 ,  H01J37/32935 ,  H01L21/67069 ,  H01L21/67253 ,  H01L22/12

Abstract: A system (1000) for characterizing an etch process, such as forming a dual damascene structure, via scatterometry based real time imaging is provided. The system (1000) includes one or more light sources (1020), each light source directing light to one or more features and/or gratings (1015) on a wafer (1010). Light reflected from the features and/or gratings (1015) is collected by a measuring system (1070), which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer (1010). The measuring system (1070) provides etching related data to a processor (1040) that determines the desirability of the etching of the respective portions of the wafer (1010). The system (1000) also includes one or more etching devices (1030), each such device corresponding to a portion of the wafer (1010) and providing for the etching thereof. The processor (1040) produces a real time etch image to characterize the progress of the etching and, in one example, produces suggested adaptations to the etch process.

Abstract translation: 提供了一种用于通过基于散射测量的实时成像来表征蚀刻过程（诸如形成双镶嵌结构）的系统（1000）。 系统（1000）包括一个或多个光源（1020），每个光源将光引导到晶片（1010）上的一个或多个特征和/或光栅（1015）。 由特征和/或光栅（1015）反射的光被测量系统（1070）收集，该测量系统处理收集的光。 收集的光表示在晶片（1010）的各个部分处获得的蚀刻结果。 测量系统（1070）将蚀刻相关数据提供给处理器（1040），处理器（1040）确定晶片（1010）的相应部分的蚀刻的合意性。 系统（1000）还包括一个或多个蚀刻装置（1030），每个这样的装置对应于晶片（1010）的一部分并提供其蚀刻。 处理器（1040）产生实时刻蚀图像以表征刻蚀的进程，并且在一个示例中，产生对刻蚀工艺的建议适配。

公开(公告)号：WO2002077570A1

公开(公告)日：2002-10-03

申请号：PCT/US2001/043805

申请日：2001-11-13

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： SINGH, Bhanwar ,  TEMPLETON, Michael, K. ,  RANGARAJAN, Bharath ,  SUBRAMANIAN, Ramkumar

IPC: G01B11/30

CPC classification number: G01B11/30 ,  G01B11/24 ,  G01B11/26 ,  G01N21/211 ,  G01N21/4738 ,  G01N21/9501

Abstract: The present invention is directed to a method (58) for detecting asymmetry in the profile of a feature (82) formed on a wafer during the process of semiconductor fabrication. The method (58) encompasses directing a beam of light or radiation at a feature (66) and detecting a reflected beam associated therewith (68). Data associated with the reflected beam is correlated with data associated with known feature profile s(19) to ascertain profile characteristics associated with the feature of interest (192). Using the profile characteristics, an asymmetry of the feature is determined (192) which is then used to generate feedback or feedforward process control data (200) to compensate for or correct such asymmetry in subsequent processing.

Abstract translation: 本发明涉及一种用于在半导体制造过程中检测在晶片上形成的特征（82）的轮廓的不对称性的方法（58）。 方法（58）包括在特征（66）处引导光束或辐射并检测与其相关联的反射光束（68）。 与反射光束相关联的数据与与已知特征轮廓s（19）相关联的数据相关，以确定与感兴趣特征相关联的轮廓特征（192）。 使用简档特征，确定特征的不对称性（192），然后将其用于生成反馈或前馈过程控制数据（200）以补偿或纠正随后处理中的这种不对称性。

公开(公告)号：WO2002037183A3

公开(公告)日：2002-05-10

申请号：PCT/US2001/051280

申请日：2001-10-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： RANGARAJAN, Bharath ,  TEMPLETON, Michael, K. ,  SUBRAMANIAN, Ramkumar

IPC: G03F7/00

Abstract: The invention provides systems and processes that form the inverse (photographic negative) of a patterned first coating. The patterned first coating is usually provided by a resist. After the first coating is removed, where appropriate, to expose the patterned first coating. The patterned first coating is subsequently removed, leaving the second coating material in the form of a pattern that is the inverse pattern of the first coating pattern. The process may be repeated with a third coating material to reproduce the pattern of the first coating in a different material. Prior to applying the second coating, the patterned first coating may be trimmed by etching, thereby reducing the feature size and producing sublithographic features. In addition to providing sublithographic features, the invention gives a simple, efficient, and high fidelity method of obtaining inverse coating patterns.