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    METHODOLOGY FOR DEVELOPING PRODUCT-SPECIFIC INTERLAYER DIELECTRIC POLISH PROCESSES
    1.
    发明申请
    METHODOLOGY FOR DEVELOPING PRODUCT-SPECIFIC INTERLAYER DIELECTRIC POLISH PROCESSES 审中-公开
    用于开发产品特定中间层电介质抛光工艺的方法

    公开(公告)号：WO1997001186A1

    公开(公告)日：1997-01-09

    申请号：PCT/US1996010563

    申请日：1996-06-18

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： ADVANCED MICRO DEVICES, INC. ,  SAHOTA, Kashmir, S. ,  AVANZINO, Steven, C.

    IPC: H01L21/66

    CPC classification number: H01L22/20 ,  H01L21/31053

    Abstract: A method for developing and characterizing a polish process for polishing an interlayer dielectric (ILD) layer (12) for a specific product or a specific patterned metal layer (14) is provided. A statistically-based model for ILD planarization by chemical mechanical polish (CMP) is used as a guide to determine, in an empirical manner, the proper amount of ILD polishing that will be required to planarize an ILD layer (12). The statistically-based model also shows the resulting ILD thicknesses to be expected. By relating the blank test wafer polished amount to the maximum amount of oxide removed from the field areas in the die and the total indicated range across the die, the ILD deposition thickness can be adjusted to attain the desired planarized ILD thickness. The attainment of local planarity, however, must be confirmed by an independent measurement technique. The polish process development methodology is extendible with respect to minimum interconnect feature size. This polish process development methodology can also be applied to products requiring mulitple planarizations for multiple levels of interconnects.

    Abstract translation: 提供了用于开发和表征用于抛光特定产品或特定图案化金属层（14）的层间电介质层（12）的抛光工艺的方法。 通过化学机械抛光（CMP）的ILD平坦化的统计学模型被用作指导，以经验方式确定平面化ILD层（12）所需的适当量的ILD抛光。 基于统计学的模型还显示了预期的ILD厚度。 通过将空白测试晶片抛光量与从模具中的场区域去除的氧化物的最大量和跨模具的总指示范围相关联，可以调节ILD沉积厚度以获得期望的平坦化ILD厚度。 然而，实现局部平面性必须通过独立的测量技术来确认。 抛光过程开发方法在最小互连特征尺寸方面是可扩展的。 这种抛光过程开发方法也可以应用于需要多层次互连的多重平面化的产品。

    CONTROLLED ANNEAL CONDUCTORS FOR INTEGRATED CIRCUIT INTERCONNECTS
    3.
    发明申请
    CONTROLLED ANNEAL CONDUCTORS FOR INTEGRATED CIRCUIT INTERCONNECTS 审中-公开

    公开(公告)号：WO2002050895A3

    公开(公告)日：2002-06-27

    申请号：PCT/US2001/050969

    申请日：2001-10-23

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： AVANZINO, Steven, C. ,  WANG, Pin-Chin, Connie ,  NGO, Minh, Van

    IPC: H01L21/768

    Abstract: A method is provided for manufacturing an integrated circuit on a semiconductor wafer (200) having a semiconductor substrate with a semiconductor device thereon. A dielectric layer is formed on the semiconductor substrate and an opening is formed in the dielectric layer. A barrier (226, 232) layer is deposited to line the opening. A seed layer (228, 234) is deposited on the barrier layer and securely bonds to the barrier layer. A conductor (230, 236) layer is deposited to fill the channel opening over the barrier layer. A planarization technique is used to planarize the barrier, seed layer, and conductor layers to be coplanar with the dielectric layer to form a conductor channel. The semiconductor wafer is then subjected to a two step timed anneal.

    SYSTEM FOR MEASURING MULTI-AXIS PRESSURE GRADIENTS IN A SEMICONDUCTOR DURING A POLISHING PROCESS
    4.
    发明申请
    SYSTEM FOR MEASURING MULTI-AXIS PRESSURE GRADIENTS IN A SEMICONDUCTOR DURING A POLISHING PROCESS 审中-公开
    用于在抛光过程中测量半导体中的多轴压力梯度的系统

    公开(公告)号：WO2003057407A1

    公开(公告)日：2003-07-17

    申请号：PCT/US2002/041412

    申请日：2002-12-23

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： RANGARAJAN, Bharath ,  AVANZINO, Steven, C. ,  SUBRAMANIAN, Ramkumar ,  SINGH, Bhanwar

    IPC: B24B37/04

    CPC classification number: B24B49/10 ,  B24B49/04

    Abstract: A system for characterizing a chemical mechanical polishing process is provided. The system includes a wafer (610) that has a metal, polysilicon, and/or dielectric layer and/or substrate and electrical resistance member(s) and/or electrical resistance entities (110) located in and/or on the metal, polysilicon and/or dielectric layer and/or substrate. The system also includes a electrical resistance monitoring system (630) that can read the wafer (610) electrical resistance(s) from the electrical resistance member(s) and/or electrical resistance entities and that can determine wafer stress(es) based upon the electrical resistance(s) to characterize the chemical mechanical polishing process. Such characterization includes producing information concerning relationships between wafer electrical resistance(s) and polishing rate, polishing uniformity and introduction of defects during polishing. Such relationships are correlated with wafer electrical resistance(s) and polishing uniformity and introduction of defects during polishing. Such relationships ips are corrlated with wafer electrical resistance(s) (e.g., wafer stress(es) as related to parameters like polishing time, pressure, speed, slurry properties and wafer/metal layer properties.

    Abstract translation: 提供了表征化学机械抛光工艺的系统。 该系统包括晶片（610），其具有金属，多晶硅和/或电介质层和/或基板和电阻元件和/或电阻实体（110），其位于金属，多晶硅和/或金属上的多晶硅 和/或电介质层和/或衬底。 该系统还包括电阻监测系统（630），其可以从电阻元件和/或电阻实体读取晶片（610）的电阻，并且可以基于以下方式确定晶片应力 表征化学机械抛光工艺的电阻。 这种表征包括产生关于晶片电阻和抛光速率之间的关系的信息，抛光均匀性和在抛光期间引入缺陷。 这种关系与晶片电阻和抛光均匀性以及在抛光过程中引入缺陷相关。 这种关系ips与晶片电阻（例如，与诸如抛光时间，压力，速度，浆料性质和晶片/金属层性质的参数相关的晶片应力）被折射。

    PROCESS FOR FORMATION OF A WIRING NETWORK USING A POROUS INTERLEVEL DIELECTRIC AND RELATED STRUCTURES
    6.
    发明申请
    PROCESS FOR FORMATION OF A WIRING NETWORK USING A POROUS INTERLEVEL DIELECTRIC AND RELATED STRUCTURES 审中-公开
    使用多个交互式电介质和相关结构形成布线网络的过程

    公开(公告)号：WO2003052794A2

    公开(公告)日：2003-06-26

    申请号：PCT/US2002/039738

    申请日：2002-12-11

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： AVANZINO, Steven, C. ,  ERB, Darrell, M. ,  WANG, Fei ,  LOPATIN, Sergey

    IPC: H01L

    CPC classification number: H01L21/02118 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7682 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A precursor (30) of a low-k porous dielectric is applied to an integrated circuit substrate (20). The precursor comprises a host thermosetting material and a porogen. Crosslinking of at least some of the first host thermosetting material is produced to form a low-k dielectric matrix (31) without decomposing all of the porogen. This leaves a solid nonporous layer of the low-k dielectric matrix. Conductive elements (36) are then inlaid in the low-k dielectric matrix. After the conductive elements are formed, remaining porogen is decomposed to leave a porous low-k dielectric layer (42). The resulting conductive elements are smooth walled.

    Abstract translation: 将低k多孔电介质的前体（30）施加到集成电路基板（20）。 前体包括主体热固性材料和致孔剂。 产生至少一些第一主体热固性材料的交联以形成低k电介质基质（31）而不分解所有的致孔剂。 这留下了低k电介质矩阵的固体无孔层。 然后将导电元件（36）镶嵌在低k电介质矩阵中。 在形成导电元件之后，剩余的致孔剂被分解以留下多孔的低k电介质层（42）。 所得到的导电元件是平滑的。

    FABRICATING A HIGH COUPLING FLASH CELL
    8.
    发明公开
    FABRICATING A HIGH COUPLING FLASH CELL 有权
    研制高耦合快闪单元的

    公开(公告)号：EP1269537A1

    公开(公告)日：2003-01-02

    申请号：EP01914573.9

    申请日：2001-02-27

    Applicant: ADVANCED MICRO DEVICES INC.

    Inventor： WANG, Larry, Yu ,  AVANZINO, Steven, C. ,  SHIELDS, Jeffrey, A. ,  PARK, Stephen, Keetai

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer (10) on a silicon substrate (12), forming an oxide (14) on the isolation formation layer (10), growing a tunnel oxide layer (16) thereon, depositing a first poly silicon layer (18), masking and etching the first poly silicon layer (18), depositing a second poly silicon layer (22) and performing a blanket etch back step, forming an oxide/nitride/oxide layer (26) forming a third poly-silicon layer (28) and depositing a silicide layer (30) thereon.

    FABRICATING A HIGH COUPLING FLASH CELL
    9.
    发明授权
    FABRICATING A HIGH COUPLING FLASH CELL 有权
    研制高耦合快闪单元的

    公开(公告)号：EP1269537B1

    公开(公告)日：2007-06-13

    申请号：EP01914573.9

    申请日：2001-02-27

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： WANG, Larry, Yu ,  AVANZINO, Steven, C. ,  SHIELDS, Jeffrey, A. ,  PARK, Stephen, Keetai

    IPC: H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11521 ,  H01L27/115

    Abstract: An article and method of manufacturing a semiconductor flash cell. The method includes producing an isolation formation layer (10) on a silicon substrate (12), forming an oxide (14) on the isolation formation layer (10), growing a tunnel oxide layer (16) thereon, depositing a first poly silicon layer (18), masking and etching the first poly silicon layer (18), depositing a second poly silicon layer (22) and performing a blanket etch back step, forming an oxide/nitride/oxide layer (26) forming a third poly-silicon layer (28) and depositing a silicide layer (30) thereon.

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