公开(公告)号：EP1125301B1

公开(公告)日：2002-10-16

申请号：EP99941220.8

申请日：1999-08-16

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： KUO, Tiao-Hua ,  KASA, Yasushi ,  LEONG, Nancy ,  CHEN, Johnny ,  VAN BUSKIRK, Michael

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A decoding circuit (54) for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder (44), a lower bank decoder (58), an upper bank decoder (56), and a plurality of flexibly partitioned conductive lines connected between the upper and lower bank decoders (56 and 58). The flexibly partitioned conductive lines (60, 62, 64, ... 74) provide a plurality of bank address pre-decoding bits for the X-decoder (44) to row decode the memory cells along the respective word lines in the memory array (20). The memory array (20) includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are connected to two Y-decoders (32 and 34) which provide column decoding for the memory cells in the upper and lower memory banks.

公开(公告)号：EP1125301A1

公开(公告)日：2001-08-22

申请号：EP99941220.8

申请日：1999-08-16

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： KUO, Tiao-Hua ,  KASA, Yasushi ,  LEONG, Nancy ,  CHEN, Johnny ,  VAN BUSKIRK, Michael

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A decoding circuit (54) for a simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises an X-decoder (44), a lower bank decoder (58), an upper bank decoder (56), and a plurality of flexibly partitioned conductive lines connected between the upper and lower bank decoders (56 and 58). The flexibly partitioned conductive lines (60, 62, 64, ... 74) provide a plurality of bank address pre-decoding bits for the X-decoder (44) to row decode the memory cells along the respective word lines in the memory array (20). The memory array (20) includes a plurality of flexibly partitioned bit lines comprising first and second bit line segments to partition the memory array into upper and lower memory banks. The bit line segments in the upper and lower memory banks are connected to two Y-decoders (32 and 34) which provide column decoding for the memory cells in the upper and lower memory banks.

公开(公告)号：EP1116238A1

公开(公告)日：2001-07-18

申请号：EP99942281.9

申请日：1999-08-16

Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

Inventor： KUO, Tiao-Hua ,  Patent Administration Department of Fujitsu Ltd ,  LEONG, Nancy ,  CHEN, Johnny ,  VAN BUSKIRK, Michael

IPC: G11C16/08 ,  G11C8/00

CPC classification number: G11C8/12 ,  G11C16/08

Abstract: A bank selector circuit for a simultaneous operation flash memory device with a flexible bank partition architecture comprises a memory boundary option (18), a bank selector encoder (2) connected to receive a memory partition indicator signal from the memory boundary option (18), and a bank selector decoder (3) connected to receive a bank selector code from the bank selector encoder (2). The decoder (3), upon receiving a memory address, outputs a bank selector output signal to point the memory address to either a lower memory bank or an upper memory bank in the simultaneous operation flash memory device, in dependence upon the selected memory partition boundary.

公开(公告)号：EP0857346A1

公开(公告)日：1998-08-12

申请号：EP96921742.0

申请日：1996-06-21

Applicant: ADVANCED MICRO DEVICES INC.

Inventor： CLEVELAND, Lee ,  CHANG, Chung, K. ,  TANG, Yuan ,  LEONG, Nancy ,  FLIESLER, Michael ,  KUO, Tiao-Hua

IPC: G11C16

CPC classification number: G11C16/3409 ,  G11C16/3404 ,  G11C16/3445

Abstract: An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.