SHORT CHANNEL FLASH EEPROM DEVICE HAVING A DOUBLE DIFFUSED SOURCE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SHORT CHANNEL FLASH EEPROM DEVICE HAVING A DOUBLE DIFFUSED SOURCE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    具有双重扩散源的短路通道闪存EEPROM器件及其制造方法

    公开(公告)号:WO1997047047A1

    公开(公告)日:1997-12-11

    申请号:PCT/US1997003229

    申请日:1997-02-28

    CPC classification number: H01L29/66825

    Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

    Abstract translation: 公开了一种用于提供具有双漫射植入结的非常短的通道存储单元的系统和方法。 该系统和方法包括提供结植入物(110),提供间隔物(108)以及提供双漫射植入物(112)的顺序步骤。 由于在间隔物之后提供双漫射植入物,所以双漫射植入物在处理之后不会延伸到存储单元的栅极之下。 因此,存储器单元具有基本上不缩短通道的有效长度的分级结。 因此,存储器单元可以随着存储器单元的尺寸减小而起作用。 此外,双漫射植入物的热循环可以与结植入物的热循环去耦合。 这是在没有使处理复杂化的情况下实现的。 因此,整体系统性能得到提高。

    METHOD FOR TIGHTENING VT DISTRIBUTION OF 5 VOLT-ONLY FLASH EEPROMS
    2.
    发明申请
    METHOD FOR TIGHTENING VT DISTRIBUTION OF 5 VOLT-ONLY FLASH EEPROMS 审中-公开
    用于强化5伏特闪存的VT分布的方法

    公开(公告)号:WO1996019810A1

    公开(公告)日:1996-06-27

    申请号:PCT/US1995014220

    申请日:1995-11-03

    CPC classification number: G11C16/3477 G11C16/16 G11C16/3468

    Abstract: There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage VT distribution after erase is obtained without sacrificing any reduction in the erase speed.

    Abstract translation: 提供了一种用于紧固闪存EEPROM器件中擦除单元的控制栅极阈值电压分布的改进方法。 在整个擦除周期期间,将相对低的正电压施加到EEPROM器件的源极区域。 施加到EEPROM器件的控制栅极的负的恒定电压的大小在整个擦除周期期间降低到预定的电压电平,以便获得更严格的阈值电压分布。 耦合在低正电压和源极区之间的负载电阻器的值同时减小到预定值,以补偿由负的恒定电压的幅度的降低引起的增加的擦除时间。 结果,在擦除之后获得改善的阈值电压VT分布,而不牺牲擦除速度的任何降低。

    METHOD FOR ELIMINATING OF CYCLING-INDUCED ELECTRON TRAPPING IN THE TUNNELING OXIDE OF 5 VOLT ONLY FLASH EEPROMS
    5.
    发明申请
    METHOD FOR ELIMINATING OF CYCLING-INDUCED ELECTRON TRAPPING IN THE TUNNELING OXIDE OF 5 VOLT ONLY FLASH EEPROMS 审中-公开
    在5伏直流闪烁的隧道氧化物中消除循环诱导电子捕获的方法

    公开(公告)号:WO1996011475A1

    公开(公告)日:1996-04-18

    申请号:PCT/US1995013012

    申请日:1995-09-29

    CPC classification number: G11C16/14

    Abstract: There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.

    Abstract translation: 提供了一种用于消除快速EEPROM装置的隧道氧化物中的循环诱导电子捕获的改进方法。 在整个擦除周期期间,相对较低的正脉冲电压被施加到EEPROM器件的源极区域。 同时,在整个擦除周期期间,向EEPROM器件的控制栅极施加负斜坡电压,从而实现从擦除周期开始到擦除周期结束的平均隧道场。

    SHORT CHANNEL FLASH EEPROM DEVICE HAVING A DOUBLE DIFFUSED SOURCE AND METHOD OF MANUFACTURING THE SAME
    7.
    发明公开
    SHORT CHANNEL FLASH EEPROM DEVICE HAVING A DOUBLE DIFFUSED SOURCE AND METHOD OF MANUFACTURING THE SAME 失效
    根据上述制造双扩散源和方法的短沟道FLAHEEPROM存储设备

    公开(公告)号:EP0934602A1

    公开(公告)日:1999-08-11

    申请号:EP97907966.0

    申请日:1997-02-28

    CPC classification number: H01L29/66825

    Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

    SHORT CHANNEL FLASH EEPROM DEVICE HAVING A DOUBLE DIFFUSED SOURCE AND METHOD OF MANUFACTURING THE SAME
    10.
    发明授权
    SHORT CHANNEL FLASH EEPROM DEVICE HAVING A DOUBLE DIFFUSED SOURCE AND METHOD OF MANUFACTURING THE SAME 失效
    根据上述制造双扩散源和方法的短沟道FLAHEEPROM存储设备

    公开(公告)号:EP0934602B1

    公开(公告)日:2004-01-02

    申请号:EP97907966.2

    申请日:1997-02-28

    CPC classification number: H01L29/66825

    Abstract: A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.

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