Abstract:
A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.
Abstract:
There is provided an improved method for tightening the distribution of control gate threshold voltages of erase cells in flash EEPROM devices. A relatively low positive voltage is applied to the source regions of the EEPROM devices during an entire erase cycle. The magnitude of a negative constant voltage applied to control gates of the EEPROM devices is lowered to a predetermined voltage level during the entire erase cycle so as to obtain a tighter threshold voltage distribution. The value of a load resistor coupled between the low positive voltage and source regions is reduced simultaneously to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage. As a result, an improved threshold voltage VT distribution after erase is obtained without sacrificing any reduction in the erase speed.
Abstract:
An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.
Abstract:
A memory device including an array of cells, where a reference current is generated by a predetermined number of reference cells disposed separate from the array of cells, the transconductance of such reference cells being equal to the transconductance of the cells of the array.
Abstract:
There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
Abstract:
An integrated circuit including an array of flash EEPROM memory cells wherein overerase correction is provided after application of each erase pulse.
Abstract:
A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.
Abstract:
There is provided an improved method for eliminating of cycling-induced electron trapping in the tunneling oxide of flash EEPROM devices. A relatively low positive pulse voltage is applied to a source region of the EEPROM devices during an entire erase cycle. Simultaneously, a negative ramp voltage is applied to a control gate of the EEPROM devices during the entire erase cycle so as to accomplish an averaging tunneling field from the beginning of the erase cycle to the end of the erase cycle.
Abstract:
A memory device including an array of cells, where a reference current is generated by a predetermined number of reference cells disposed separate from the array of cells, the transconductance of such reference cells being equal to the transconductance of the cells of the array.
Abstract:
A system and method for providing a very short channel memory cell having a double diffuse implant junction is disclosed. The system and method comprise the sequential steps of providing a junction implant (110), providing a spacer (108), and providing a double diffuse implant (112). Because the double diffuse implant is provided after the spacer, the double diffuse implant does not extend as far under the gate of a memory cell after processing. Thus, the memory cell has a graded junction that does not substantially shorten the effective length of the channel. The memory cell can, therefore, function even as the size of the memory cell is decreased. In addition, the thermal cycling of the double diffuse implant may be decoupled from that of the junction implant. This is achieved without complicating processing. Consequently, overall system performance is enhanced.