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    BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING
    2.
    发明申请
    BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING 审中-公开
    非易失性存储器的银行架构启用同时读取和写入

    公开(公告)号：WO1998028750A1

    公开(公告)日：1998-07-02

    申请号：PCT/US1997020819

    申请日：1997-11-13

    Applicant: ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED

    Inventor： ADVANCED MICRO DEVICES, INC. ,  FUJITSU LIMITED ,  CHEN, Johnny, C. ,  CHANG, Chung, K. ,  KUO, Tiao-Hua ,  AKAOGI, Takao

    IPC: G11C16/06

    CPC classification number: G11C16/10 ,  G11C2216/22

    Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation.

    Abstract translation: 闪存器件分为两个或更多个存储体。 每个银行都包括一些行业。 每个扇区包括闪存单元。 每个存储体都有一个解码器，可选择性地从输入地址缓冲区或内部地址定序器接收由内部状态机控制的地址。 每个存储体的输出数据可以传送到读出读出放大器或验证读出放大器。 读出放大器连接到输出缓冲器，而验证放大器连接到状态机。 当一个银行收到一个写命令时，内部状态机接受控制并启动程序或擦除操作。 当一个银行忙于编程或擦除操作时，可以访问另一个存储体进行读取操作。

    SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
    3.
    发明公开
    SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE 有权
    具有灵活的内存BANK分类法同时闪存

    公开(公告)号：EP1116239A1

    公开(公告)日：2001-07-18

    申请号：EP99946599.0

    申请日：1999-08-16

    Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

    Inventor： KUO, Tiao-Hua ,  KASA, Yasushi ,  LEONG, Nancy ,  CHEN, Johnny ,  VAN BUSKIRK, Michael

    IPC: G11C16/08 ,  G11C8/00 ,  G11C7/18

    CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/12

    Abstract: A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array (20) including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines (28 and 30) each connected to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder (22) connected to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders (24 and 26) are connected to the X-decoder (22). Two Y-decoders (32 and 34) are connected to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

    BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING
    4.
    发明公开
    BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING 失效
    为了与可能性非易失性存储器的银行体系结构，阅读及注册GLEICHZEITIEN

    公开(公告)号：EP0944907A1

    公开(公告)日：1999-09-29

    申请号：EP97947516.0

    申请日：1997-11-13

    Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

    Inventor： CHEN, Johnny, C. ,  CHANG, Chung, K. ,  KUO, Tiao-Hua ,  AKAOGI, Takao

    IPC: G11C16

    CPC classification number: G11C16/10 ,  G11C2216/22

    Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation.

    BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING
    7.
    发明授权
    BANK ARCHITECTURE FOR A NON-VOLATILE MEMORY ENABLING SIMULTANEOUS READING AND WRITING 失效
    银行体系结构与用于同时读取登记的可能性非易失性存储器

    公开(公告)号：EP0944907B1

    公开(公告)日：2001-10-17

    申请号：EP97947516.7

    申请日：1997-11-13

    Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

    Inventor： CHEN, Johnny, C. ,  CHANG, Chung, K. ,  KUO, Tiao-Hua ,  AKAOGI, Takao

    IPC: G11C16/06

    CPC classification number: G11C16/10 ,  G11C2216/22

    Abstract: A flash memory device is divided into two or more banks. Each bank includes a number of sectors. Each sector includes flash memory cells. Each bank has a decoder that selectively receives an address from an input address buffer or from an internal address sequencer controlled by an internal state machine. The output data for each bank can be communicated to a read sense amplifier or a verify sense amplifier. The read sense amplifier connects to the output buffer while the verify sense amplifier connects to the state machine. When one bank receives a write command, the internal state machine takes control and starts the program or erase operation. While one bank is busy with a program or erase operation, the other bank can be accessed for a read operation.

    SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE
    8.
    发明授权
    SIMULTANEOUS OPERATION FLASH MEMORY DEVICE WITH A FLEXIBLE BANK PARTITION ARCHITECTURE 有权
    具有灵活的内存BANK分类法同时闪存

    公开(公告)号：EP1116239B1

    公开(公告)日：2002-05-15

    申请号：EP99946599.0

    申请日：1999-08-16

    Applicant: ADVANCED MICRO DEVICES INC. ,  FUJITSU LIMITED

    Inventor： KUO, Tiao-Hua ,  KASA, Yasushi ,  LEONG, Nancy ,  CHEN, Johnny ,  VAN BUSKIRK, Michael

    IPC: G11C16/08 ,  G11C8/00 ,  G11C7/18

    CPC classification number: G11C16/08 ,  G11C7/18 ,  G11C8/12

    Abstract: A simultaneous operation non-volatile memory device with a flexible bank partition architecture comprises a memory array (20) including a plurality of memory cells arranged in a plurality of columns and rows, a plurality of bit lines (28 and 30) each connected to a respective column of the memory cells, each of the bit lines comprising first and second bit line segments separated by a gap designating a memory partition boundary between upper and lower memory banks, and an X-decoder (22) connected to the respective rows of the memory cells to row decode the memory array in response to receiving upper and lower bank memory addresses. Two pre-decoders (24 and 26) are connected to the X-decoder (22). Two Y-decoders (32 and 34) are connected to the bit line segments to provide column decoding for the memory cells in the upper and lower memory banks, respectively.

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