公开(公告)号：EP3213609A1

公开(公告)日：2017-09-06

申请号：EP15854911.3

申请日：2015-10-07

Applicant: ATI Technologies ULC

Inventor： TOPACIO, Roden ,  LEUNG, Andrew Kw

IPC: H05K3/40 ,  H05K3/28 ,  H05K3/36 ,  H05K3/42

CPC classification number: H01L23/49816 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a solder mask on a circuit board with a first opening that has a sidewall. A solder interconnect pad is formed in the first opening. The sidewall sets the lateral extent of the solder interconnect pad.

Abstract translation: 公开了各种电路板及其制造方法。 在一个方面中，提供了一种制造方法，其包括在具有侧壁的第一开口的电路板上形成焊接掩模。 在第一开口中形成焊料互连焊盘。 侧壁设定焊料互连焊盘的横向范围。

公开(公告)号：EP2471096A1

公开(公告)日：2012-07-04

申请号：EP10824354.4

申请日：2010-10-21

Applicant: ATI Technologies ULC

Inventor： TOPACIO, Roden ,  WONG, Gabriel

IPC: H01L23/488 ,  H01L23/50

CPC classification number: H01L23/49816 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05599 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes pads for attaching solder bumps; bond-pads bonded to bump-pads of a die having an integrated circuit, and traces interconnecting bond-pads to pads. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces at least partially surrounding some pads so as to absorb stress from solder bumps attached to the pads. Parts of the traces that surround pads protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

公开(公告)号：EP2057672B1

公开(公告)日：2020-06-03

申请号：EP07841549.4

申请日：2007-08-29

Applicant: ATI Technologies ULC

Inventor： McLELLAN, Neil ,  CHAN, Vincent ,  TOPACIO, Roden

IPC: H01L21/56 ,  H01L21/68 ,  H01L21/683 ,  H01L23/16 ,  H01L23/00

公开(公告)号：EP2269216A1

公开(公告)日：2011-01-05

申请号：EP09721759.0

申请日：2009-03-19

Applicant: ATI Technologies ULC

Inventor： TOPACIO, Roden ,  ZBRZEZNY, Adam

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/31

CPC classification number: H01L23/3128 ,  H01L23/16 ,  H01L23/562 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/09136 ,  H05K2201/09781 ,  H05K2203/043 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Various semiconductor chip package substrates with reinforcement and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes providing a package substrate that has a first side and a second side opposite to the first side. The first side has a central area adapted to receive a semiconductor chip. A solder reinforcement structure is formed on the first side of the package substrate outside of the central area to resist bending of the package substrate.

公开(公告)号：EP2229694A2

公开(公告)日：2010-09-22

申请号：EP08855955.4

申请日：2008-12-04

Applicant: ATI Technologies ULC

Inventor： MCLELLAN, Neil ,  LI, Yue ,  TOPACIO, Roden ,  CHEUNG, Terence

IPC: H01L23/485 ,  H01L21/60 ,  H01L23/525

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/50 ,  H01L23/525 ,  H01L23/5286 ,  H01L24/11 ,  H01L2224/10126 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/1148 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/1411 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12044 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

Abstract: Various semiconductor chip conductor structures and methods of fabricating the same are provided. In one aspect, a method of manufacturing is provided that includes forming a conductor structure on a semiconductor chip. The conductor structure has a first site electrically connected to a first redistribution layer structure and a second site electrically connected to a second redistribution layer structure. A solder structure is formed on the conductor structure.

公开(公告)号：EP2460393B1

公开(公告)日：2017-10-11

申请号：EP10803777.1

申请日：2010-07-28

Applicant: ATI Technologies ULC

Inventor： LEUNG, Andrew ,  TOPACIO, Roden ,  MARTINEZ, Liane ,  LOW, Yip Seng

IPC: H05K3/00 ,  H01L23/12 ,  H01L23/488 ,  H05K1/02 ,  H05K3/10

CPC classification number: H01L23/49822 ,  B32B37/02 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/00 ,  H01L21/4857 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09136 ,  Y10T29/49117 ,  Y10T156/10 ,  H01L2224/05599

公开(公告)号：EP2700091A1

公开(公告)日：2014-02-26

申请号：EP12773917.5

申请日：2012-04-23

Applicant: ATI Technologies ULC

Inventor： TOPACIO, Roden ,  WONG, Gabriel

IPC: H01L21/71 ,  H01L23/488

CPC classification number: H01L24/17 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/33 ,  H01L2224/0233 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05008 ,  H01L2224/05012 ,  H01L2224/05013 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05022 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/05559 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/1132 ,  H01L2224/13007 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01028 ,  H01L2924/01031

Abstract: A routing layer for a semiconductor die is disclosed. The routing layer includes traces interconnecting integrated circuit bond-pads to UBMs. The routing layer is formed on a layer of dielectric material. The routing layer includes conductive traces arranged underneath the UBMs as to absorb stress from solder bumps attached to the UMBs. Traces beneath the UBMs protect parts of the underlying dielectric material proximate the solder bumps, from the stress.

公开(公告)号：EP2545755A1

公开(公告)日：2013-01-16

申请号：EP11752774.7

申请日：2011-03-09

Applicant: ATI Technologies ULC

Inventor： TOPACIO, Roden

IPC: H05K3/36 ,  H05K3/10

CPC classification number: H05K3/3452 ,  H01L21/563 ,  H01L23/28 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13111 ,  H01L2224/16237 ,  H01L2224/2929 ,  H01L2224/29386 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81455 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/2072 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49155 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01082 ,  H01L2224/05552 ,  H01L2924/00

Abstract: Various circuit boards and methods of manufacturing using the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a solder mask to a side of a circuit board and forming at least one opening in the solder mask leading to the side. An underfill is placed on the solder mask so that a portion thereof projects into the at least one opening.

Abstract translation: 公开了各种电路板及使用其的制造方法。 在一个方面中，提供了一种制造方法，其包括将焊料掩模施加到电路板的一侧并在通向该侧的阻焊掩模中形成至少一个开口。 将底部填充物放置在阻焊层上，使得其一部分伸入至少一个开口中。

公开(公告)号：EP2460393A1

公开(公告)日：2012-06-06

申请号：EP10803777.1

申请日：2010-07-28

Applicant: ATI Technologies ULC

Inventor： LEUNG, Andrew ,  TOPACIO, Roden ,  MARTINEZ, Liane ,  LOW, Yip Seng

IPC: H05K3/00 ,  H01L23/12 ,  H01L23/488 ,  H05K1/02 ,  H05K3/10

CPC classification number: H01L23/49822 ,  B32B37/02 ,  B32B2309/105 ,  B32B2310/0843 ,  B32B2457/00 ,  H01L21/4857 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09136 ,  Y10T29/49117 ,  Y10T156/10 ,  H01L2224/05599

Abstract: A method of manufacturing a substrate for use in electronic packaging having a core, m buildup layers on a first surface of the core and n buildup layers on a second surface of the core, where m ≠ n is disclosed. The method includes forming (m-n) of the m buildup layers on the first surface, and then forming n pairs of buildup layers, with each one of the pairs including one of the n buildup layers formed on the second surface and one of the remaining n of the m buildup layers formed on the first surface. Each buildup layer includes a dielectric layer and a conductive layer formed thereon. The disclosed method protects the dielectric layer in each of buildup layers from becoming overdesmeared during substrate manufacturing by avoiding repeated desmearing of dielectric materials.

Abstract translation: 制造中使用的基板在电子封装具有在所述芯的第二表面，其中m≠N在芯和n堆积层的第一表面上的芯，m层积层的方法，是游离缺失盘。 该方法包括形成在第一表面上的m层积层的（M-N），然后形成堆积层的n对，与对包括形成在第二表面上的n层积层中的一个和中的一个中的每一个 形成在第一表面上的m层积层的剩余的n。 每个堆积层包括介电层和导电形成于其上的层。 盘方法游离缺失从通过避免电介质材料的重复去钻污底物的制造期间被overdesmeared保护在堆积层的介电层。

公开(公告)号：EP2057672A1

公开(公告)日：2009-05-13

申请号：EP07841549.4

申请日：2007-08-29

Applicant: ATI Technologies ULC

Inventor： MCLELLAN, Neil ,  CHAN, Vincent ,  TOPACIO, Roden

IPC: H01L21/56 ,  H01L21/68

Abstract: A method of packaging a plurality of semiconductor chips comprises: providing a substrate panel having a first coefficient of thermal expansion (CTE); providing a carrier having a second CTE that is less than the first CTE; heating the substrate panel and the carrier to first and second elevated temperatures respectively; mounting the substrate panel at about the first elevated temperature to the carrier, the carrier being at said second elevated temperature, to provide a connection between the carrier and the substrate panel; and cooling the carrier and the substrate panel from the first and second elevated temperatures thereby putting the substrate panel into tension in at least one direction. A stiffener panel may be affixed to the substrate panel and heated to an elevated temperature and while the substrate panel is heated to an elevated temperature. A plurality of dies may be mounted and electrically connected to the substrate panel. Under-filling of the plurality of dies may occur with the stiffener panel affixed to the substrate panel.

Abstract translation: 包装多个半导体芯片的方法包括：提供具有第一热膨胀系数（CTE）的基板; 提供具有小于第一CTE的第二CTE的载体; 将基板和载体分别加热到第一和第二升高温度; 将所述基板面板在所述第一升高温度下安装到所述载体，所述载体处于所述第二升高温度，以在所述载体和所述基板面板之间提供连接; 以及从所述第一和第二升高的温度冷却所述载体和所述基板，从而使所述基板在至少一个方向上处于张力状态。 加强板可以固定到基板面板上并被加热到升高的温度，同时将基板面板加热到升高的温度。 多个管芯可以被安装并电连接到衬底面板。 多个模具的欠填充可以在加强板固定到基板上的情况下发生。