公开(公告)号：HK1033216A1

公开(公告)日：2001-08-17

申请号：HK01103929

申请日：2001-06-07

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  PATHAK SAROJ ,  ROSENDALE GLEN A ,  PAYNE JAMES E ,  HANGZO NIANGLAMCHING

IPC: H03K17/22 ,  H03L

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

公开(公告)号：NO990229A

公开(公告)日：1999-03-19

申请号：NO990229

申请日：1999-01-19

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/22 ,  G11C16/28 ,  G11C

CPC classification number: G11C16/22 ,  G11C16/28

公开(公告)号：NO319753B1

公开(公告)日：2005-09-12

申请号：NO985933

申请日：1998-12-17

Applicant: ATMEL CORP A DELAWARE CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00 ,  G11C7/00 ,  G11C11/34 ,  G11C15/00

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

公开(公告)号：DE69825837T2

公开(公告)日：2005-09-01

申请号：DE69825837

申请日：1998-04-22

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories. The bit line voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.

公开(公告)号：HK1046983A1

公开(公告)日：2003-01-30

申请号：HK02108172

申请日：2002-11-12

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PAYNE JAMES E ,  PATHAK JAGDISH

IPC: G11C7/06 ,  G11C16/06 ,  G11C7/14 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

公开(公告)号：NO20020847D0

公开(公告)日：2002-02-21

申请号：NO20020847

申请日：2002-02-21

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PAYNE JAMES E ,  PATHAK JAGDISH

IPC: G11C7/06 ,  G11C16/06 ,  G11C7/14 ,  G11C16/04 ,  G11C16/28 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C

Abstract: A reference cell for use in a high speed sensing circuit includes a first sub-circuit and a second sub-circuit. The first sub-circuit has a structure similar to memory cells within odd number rows of a main memory array. The second sub-circuit has a structure similar to memory cells within even numbered rows of the main memory array. If a target cell within the main memory array lies within an odd numbered row, then the first sub-circuit is selected, and if the target cell lies within an even numbered row, then second sub-circuit is selected. Both of the first and second sub-circuits include a reference transistors having its control gate broken into two parts. A first part is a poly 1 layer and is separated from the channel region by a tunneling oxide. A second part is a metal or poly 2 layer over the first part and separated from the first part by a gate oxide. A via is used to connect the first part to the second part.

公开(公告)号：NO20002194D0

公开(公告)日：2000-04-27

申请号：NO20002194

申请日：2000-04-27

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH ,  PATHAK SAROJ ,  ROSENDALE GLEN A ,  PAYNE JAMES E ,  HANGZO NIANGLAMCHING

IPC: H03K17/22 ,  H03L

Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.

公开(公告)号：NO990229L

公开(公告)日：1999-03-19

申请号：NO990229

申请日：1999-01-19

Applicant: ATMEL CORP

Inventor： PATHAK SAROJ ,  PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/22 ,  G11C16/28 ,  G11C

Abstract: A memory device includes a memory cell whose data state is sensed by a sense amplifier. A balance amplifier having the same construction as the sense amplifier is utilized to sense a balance cell having the same construction as the memory cell. The balance cell is maintained in an erased (conductive) state. The balance cell is gated by the output of the sense amplifier. Such a device operates in a way to consume the same amount of power regardless of the data state of the memory cell. In one embodiment of the invention, a memory device consisting of a memory array includes a balance circuit associated with each of the sense amplifiers in the memory device. In another embodiment of the invention, a trim circuit is used to adjust the conductivity of the of the balance circuit. This allows the balance circuit to be fine tuned during manufacture to compensate for process variations, thus allowing the balance circuit to be matched to the memory cells.

公开(公告)号：NO985933A

公开(公告)日：1999-02-22

申请号：NO985933

申请日：1998-12-17

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00 ,  G11C

CPC classification number: G11C16/24

公开(公告)号：CA2258957A1

公开(公告)日：1998-10-29

申请号：CA2258957

申请日：1998-04-22

Applicant: ATMEL CORP

Inventor： PATHAK JAGDISH

IPC: G11C16/06 ,  G11C16/24 ,  G11C17/00 ,  G11C8/00 ,  G11C14/00 ,  G11C16/00 ,  G11C11/40

Abstract: The present invention relates to a bit line clamping scheme for non-volatile memories (10). The bit line (35) voltage is maintained at a desired voltage level so as to avoid read disturb effects, while being independent of power supply variations and consuming virtually no power. The invention makes practical memory devices which are designed for both high voltage (5 volt) operation and low voltage (3.3 and 2.5 volt) operation.