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公开(公告)号：WO0077529A3
公开(公告)日：2001-06-28
申请号：PCT/US0014189
申请日：2000-05-23
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , ROSENDALE GLEN A , HANGZO NIANGLAMCHING
CPC classification number: G11C29/02 , G01R31/31855
Abstract: A video chip (100) includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register (122, 124). There is a circuit for the column lines (114) and for the row lines (112). A bit pattern is driven onto the column (114) or the row lines (112) and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.
Abstract translation: 视频芯片（100）包括用于检测开路和短路的测试电路。 电路包括串联连接的晶体管链和测试寄存器（122,124）。 存在用于列线（114）和行线（112）的电路。 位图被驱动到列（114）或行线（112）上并被接收在相应的测试电路中。 该模式被读出并与输入模式进行比较以检测故障线路。
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公开(公告)号：WO0077529B1
公开(公告)日：2001-08-16
申请号：PCT/US0014189
申请日：2000-05-23
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , ROSENDALE GLEN A , HANGZO NIANGLAMCHING
CPC classification number: G11C29/02 , G01R31/31855
Abstract: A video chip (100) includes test circuitry for detecting opens and shorts. The circuitry includes a series-connected chain of transistors and a test register (122, 124). There is a circuit for the column lines (114) and for the row lines (112). A bit pattern is driven onto the column (114) or the row lines (112) and received in the corresponding test circuitry. The pattern is read out and compared against the input pattern to detect faulty lines.
Abstract translation: 视频芯片（100）包括用于检测开路和短路的测试电路。 该电路包括串联的晶体管链和测试寄存器（122,124）。 存在用于列线（114）和用于行线（112）的电路。 位模式被驱动到列（114）或行线（112）上并被接收在相应的测试电路中。 读出模式并与输入模式进行比较以检测故障线路。
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公开(公告)号：EP1034619A4
公开(公告)日：2003-09-10
申请号：EP98958071
申请日：1998-11-20
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH , PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
IPC: H03K17/22
CPC classification number: H03K17/223
Abstract: A power-on-reset circuit includes a first charging stage (162) for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means (122) for charging up a second charging stage (164). When the second charging stage reaches a first voltage level, a circuit (130) is tripped to pull the potential of the first to ground. The grounding of the first charging stage (162) is fed back to the charging means (122) which shuts off its power burning components and maintains the first voltage level at the second charging stage (164).
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4.发明公开
公开(公告)号：EP1086449A4
公开(公告)日：2003-08-27
申请号：EP99925798
申请日：1999-05-25
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , ROSENDALE GLEN A , HANGZO NIANGLAMCHING
CPC classification number: G09G3/3688 , G09G3/2011 , G09G3/2074 , G09G3/3677 , G09G2300/0876 , G09G2310/0289
Abstract: A circuit (202; 204) for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor (308; 308') powered by a high voltage power source to bias a pass transistor (114; 124) at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor (304; 304') provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor (306; 306') operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.
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5.发明公开
公开(公告)号：EP1078370A4
公开(公告)日：2001-07-04
申请号：EP99914242
申请日：1999-03-29
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
CPC classification number: G11C7/062 , G11C7/065 , G11C7/1036
Abstract: A sense amplifier (200) for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controlled manner (270), in response to a control pulse (SAEN). The control pulse (SAEN) is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps (200) are utilized to read out in parallel fashion the N memory cells (bits) comprising an accessed memory location. The sense amps (200) are therefore active only of a period of time sufficient to read out a memory cell.
Abstract translation: 响应于控制脉冲（SAEN），在串行配置存储器中使用的读出放大器（200）包括以受控方式启用和禁用（270）的多个级。 控制脉冲（SAEN）是在外部提供的时钟信号的每N个周期产生的，该时钟用于输出代表存储器装置内容的比特流。 在优选实施例中，利用N个这样的读出放大器（200）以并行方式读出包括被访问的存储器位置的N个存储器单元（位）。 因此，读出放大器（200）仅在足以读出存储单元的时间段内有效。
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Patent Agency Ranking
公开(公告)号：EP0954864A4
公开(公告)日：2001-01-31
申请号：EP98960402
申请日：1998-11-19
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
CPC classification number: G11C7/1039
Abstract: A serial configuration memory device (100) comprises an architecture wherein the reading out of data and the outputting (52) of the bitstream are performed in pipeline fashion. As a result, the device is capable of outputting a bitstream based solely on the frequency of an externally provided clock, and is not limited by the slower operating speed of the sense amp circuitry. A caching scheme (34 and 44) is provided which allows the first byte to be pre-loaded during a reset cycle so that the device can immediately begin outputting the bitstream as soon as the reset cycle completes. In a preferred embodiment of the invention, the bitstream consists of serially accessed memory locations starting from memory location zero. In one variation, the bitstream can begin from a memory location other than memory location zero.
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公开(公告)号：MY136005A
公开(公告)日：2008-07-31
申请号：MYPI20002618
申请日：2000-06-09
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , ROSENDALE GLEN A , HANGZO NIANGLAMCHING
Abstract: A VIDEO CHIP (100) INCLUDES TEST CIRCUITRY FOR DETECTING OPENS (702) AND SHORTS (704).THE CIRCUITRY INCLUDES A SERIES-CONNECTED CHAIN: OF TRANSISTORS (202) AND A TEST REGISTER. THERE IS A CIRCUIT FOR THE COLUMN LINES (114) AND FOR THE ROW LINES (112). A BIT PATTERN IS DRIVEN ONTO THE COLUMN (114) OR THE ROW (112) LINES AND RECEIVED IN THE CORRESPONDING TEST CIRCUITRY. THE PATTERN IS READ OUT AND COMPARED AGAINST THE INPUT PATTERN TO DETECT FAULTY LINES.(FIG 1)
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公开(公告)号：HK1035952A1
公开(公告)日：2001-12-14
申请号：HK01106545
申请日：2001-09-17
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , PAYNE JAMES E , ROSENDALE GLEN A , HANGZO NIANGLAMCHING
Abstract: A circuit for transferring high voltage analog video signals while enabling the use of conventional low voltage logic levels includes a first transistor powered by a high voltage power source to bias a pass transistor at a high voltage level. The pass transistor receives a high voltage video signal and because of the high voltage bias is able to pass the video signal without attenuation of the signal due to feedthrough effects, thus preserving the fidelity of the video signal. A second transistor provides a ground potential which operates to turn OFF the pass transistor, thus disabling the transfer of the video signal therethrough. A third transistor operatively coupled to the first transistor operates to turn OFF the first transistor when the second transistor is in operation.
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公开(公告)号：HK1035064A1
公开(公告)日：2001-11-09
申请号：HK01105529
申请日：2001-08-09
Applicant: ATMEL CORP
Inventor： PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
Abstract: A sense amplifier for use in a serial configuration memory includes multiple stages which are enabled and disabled in a controller manner, in response to a control pulse. The control pulse is produced every Nth period of an externally provided clock signal, the clock being used to clock out a bitstream representing the contents of the memory device. In a preferred embodiment, N such sense amps are utilized to read out in parallel fashion the N memory cells (bits) that constitute an accessed memory location. The sense amps are therefore active only of a period of time sufficient to read out a memory cell.
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公开(公告)号：NO20002194D0
公开(公告)日：2000-04-27
申请号：NO20002194
申请日：2000-04-27
Applicant: ATMEL CORP
Inventor： PATHAK JAGDISH , PATHAK SAROJ , ROSENDALE GLEN A , PAYNE JAMES E , HANGZO NIANGLAMCHING
Abstract: A power-on-reset circuit includes a first charging stage for building up a charge during power up. The rising voltage of the first charging stage is sensed and used to control means for charging up a second charging stage. When the second charging stage reaches a first voltage level, a circuit is tripped to pull the potential of the first to ground. The grounding of the first charging stage is fed back to the charging means which shuts off its power burning components and maintains the first voltage level at the second charging stage.
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