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公开(公告)号:US11853140B2
公开(公告)日:2023-12-26
申请号:US17676683
申请日:2022-02-21
Applicant: Apple Inc.
Inventor: Doron Rajwan , Karl Daniel Wulcan , Tal Kuzi , Inder M. Sodhi , Achmed R. Zahir
IPC: G06F1/3206 , G06F1/324 , G06F1/3228 , G06F1/3293 , G06F1/3296
CPC classification number: G06F1/3206 , G06F1/324 , G06F1/3228 , G06F1/3293 , G06F1/3296
Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).
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公开(公告)号:US11693472B2
公开(公告)日:2023-07-04
申请号:US17676668
申请日:2022-02-21
Applicant: Apple Inc.
Inventor: Ilya Granovsky , Doron Rajwan , Tal Kuzi , Nir Leshem , Lior Zimet
IPC: G06F1/32 , G06F1/324 , G06F1/3206
CPC classification number: G06F1/324 , G06F1/3206
Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.
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公开(公告)号:US20230077747A1
公开(公告)日:2023-03-16
申请号:US17572664
申请日:2022-01-11
Applicant: Apple Inc.
Inventor: Doron Rajwan , Craig S Forbell , Jamie L Langlinais
IPC: G05F1/46
Abstract: An apparatus includes hardware circuits, a front-end power supply, voltage regulators, and control circuitry. The front-end power supply generates electrical power for the hardware circuits. The front-end power supply includes power stages that generate portions of electrical power and are activated and deactivated independently. The voltage regulators are connected to an output of the front-end power supply and provide adjustable operating voltages to the hardware circuits. The control circuitry controls the voltage regulators to supply the adjustable operating voltages responsively to requests from the hardware circuits, compares the adjustable operating voltages to settings that are specified as safe for provisioning by a predefined partial number of the power stages of the front-end power supply, and adaptively activates and deactivates the power stages, including ensuring that a number of active power stages is set to the predefined partial number only while the operating voltages match the safe settings.
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公开(公告)号:US20220357784A1
公开(公告)日:2022-11-10
申请号:US17313837
申请日:2021-05-06
Applicant: Apple Inc.
Inventor: Doron Rajwan , Karl Daniel Wulcan , Lital Levy-Rubin , Tal Kuzi
IPC: G06F1/3206 , G06F11/30 , G06F11/34
Abstract: Systems, apparatuses, and methods for implementing telemetry push aggregation techniques are described. A computing system includes one or more input/output (I/O) agents interposed between functional units and a communication fabric. A given I/O agent receives a set of aggregation rules from a power management unit. The I/O agent monitors traffic from the functional units, and the I/O agent generates telemetry data from the traffic data based on the set of aggregation rules. The telemetry data is used by the power management unit to make adjustments to one or more power settings.
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公开(公告)号:US20250103117A1
公开(公告)日:2025-03-27
申请号:US18392736
申请日:2023-12-21
Applicant: Apple Inc.
Inventor: Doron Rajwan , Jamie L. Langlinais , Jan Krellner
IPC: G06F1/26
Abstract: Techniques are disclosed relating to managing power allocation for component circuits coupled to one or more power sources. A system can include a plurality of component circuits, a plurality of power sources, and a power splitter circuit. The power splitter circuit may access, from programmable registers, a mapping between ones of the plurality of component circuits and ones of the plurality of power sources. The power splitter circuit may then allocate power to a given one of the plurality of component circuits based on one or more power budgets of one or more power sources that are mapped to the given component circuit as indicated by the mapping. In various cases, the power splitter circuit may determine that multiple power sources supply power to a particular component circuit and allocate power to the particular component circuit based on respective power budgets of the multiple power sources.
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公开(公告)号:US11836107B2
公开(公告)日:2023-12-05
申请号:US17683396
申请日:2022-03-01
Applicant: Apple Inc.
Inventor: Doron Rajwan , Lior Zimet , Sagi Lahav
CPC classification number: G06F15/7807 , G06F13/4013
Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.
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公开(公告)号:US20230109984A1
公开(公告)日:2023-04-13
申请号:US17573274
申请日:2022-01-11
Applicant: Apple Inc.
Inventor: Doron Rajwan , Inder M. Sodhi , Keith Cox , Jung Wook Cho , Kevin I. Park , Tal Kuzi
IPC: G06F1/3234 , G06F1/3206
Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.
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公开(公告)号:US20230061898A1
公开(公告)日:2023-03-02
申请号:US17676683
申请日:2022-02-21
Applicant: Apple Inc.
Inventor: Doron Rajwan , Karl Daniel Wulcan , Tal Kuzi , Inder M. Sodhi , Achmed R. Zahir
IPC: G06F1/3293 , G06F1/3228
Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on a chip) may modify power budgets for various components in the integrated circuit to reduce the amount of power control caused by external signaling that indicates a voltage regulator overload (e.g., a voltage droop).
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公开(公告)号:US11303478B2
公开(公告)日:2022-04-12
申请号:US17164482
申请日:2021-02-01
Applicant: Apple Inc.
Inventor: Luca O. Iuliano , Doron Rajwan , Ali Rabbani Rankouhi
Abstract: An apparatus includes a decoding circuit, and a communication bus that is configured to transfer a particular data payload and a control signal that indicates whether the particular data payload includes a mask value. The mask value is indicative of enabled and non-enabled data words in the particular data payload. The decoding circuit is configured to receive, from an encoding circuit via the communication bus, the particular data payload and the control signal. In response to a determination that the control signal indicates that the particular data payload does not include the mask value, the decoding circuit is configured to use a default value for the mask value, and to create an uncompressed data payload from the particular data payload using the default value, wherein the default value causes the decoding circuit to maintain positions of data words between the particular data payload and the uncompressed data payload.
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公开(公告)号:US20250103121A1
公开(公告)日:2025-03-27
申请号:US18392770
申请日:2023-12-21
Applicant: Apple Inc.
Inventor: Doron Rajwan , Jamie L. Langlinais , Kevin I. Park
IPC: G06F1/3206
Abstract: Techniques are disclosed relating to managing power allocation for component circuits coupled to one or more power sources. A system can include a first integrated circuit die that is indirectly coupled to a second integrated circuit die through a set of intervening integrated circuit dies. The system can include a first power source configured to supply power to component circuits of the first and second integrated circuit dies. The first integrated circuit may allocate, to a first set of component circuits of the first integrated circuit die, a first set of power credits for obtaining power from the first power source. The first integrated circuit may send a second set of power credits to the second integrated circuit die through the set of intervening integrated circuit dies without the set of intervening integrated circuit dies using the second set of power credits to obtain power from the first power source.
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