公开(公告)号：US20230060508A1

公开(公告)日：2023-03-02

申请号：US17462374

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Elli Bagelman

IPC: G06F9/46 ,  G06F9/50 ,  G06F13/16

Abstract: A memory controller with a separate transaction table for real-time transactions is disclosed. A system includes a plurality of agents and a memory controller configured to receive real-time and non-real-time memory requests from ones of the plurality of agents. The memory controller includes a real-time incoming transaction table configured to store those memory requests received from a subset of the plurality of agents that are real-time memory requests, and a non-real-time incoming transaction table configured to store those memory requests received from the subset of the plurality of agents that are non-real-time memory requests. The memory controller further includes an arbitration circuit configured to select a memory request from among memory requests stored in the real-time and non-real-time incoming transaction tables and further configured to enforce a quality of service policy for the real-time memory requests.

公开(公告)号：US20240241561A1

公开(公告)日：2024-07-18

申请号：US18622481

申请日：2024-03-29

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Karl D. Wulcan ,  Tal Kuzi ,  Inder M. Sodhi ,  Achmed R. Zahir ,  Ilya Granovsky ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3296

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Trigger logic circuits and rate control circuits may be implemented in combination with a power management circuit to control power provided to components of the integrated circuits. Power may be controlled based on receiving trigger signals from a power management unit. The power management circuit may implement power budgets for various components in the integrated circuits.

公开(公告)号：US11900146B2

公开(公告)日：2024-02-13

申请号：US17462374

申请日：2021-08-31

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Elli Bagelman

IPC: G06F9/46 ,  G06F13/16 ,  G06F9/50

CPC classification number: G06F9/467 ,  G06F9/5016 ,  G06F13/1605 ,  G06F2209/5011

Abstract: A memory controller with a separate transaction table for real-time transactions is disclosed. A system includes a plurality of agents and a memory controller configured to receive real-time and non-real-time memory requests from ones of the plurality of agents. The memory controller includes a real-time incoming transaction table configured to store those memory requests received from a subset of the plurality of agents that are real-time memory requests, and a non-real-time incoming transaction table configured to store those memory requests received from the subset of the plurality of agents that are non-real-time memory requests. The memory controller further includes an arbitration circuit configured to select a memory request from among memory requests stored in the real-time and non-real-time incoming transaction tables and further configured to enforce a quality of service policy for the real-time memory requests.

公开(公告)号：US20230063331A1

公开(公告)日：2023-03-02

申请号：US17676668

申请日：2022-02-21

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Doron Rajwan ,  Tal Kuzi ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/324 ,  G06F1/3206

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.

公开(公告)号：US20250094330A1

公开(公告)日：2025-03-20

申请号：US18404822

申请日：2024-01-04

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Lital Levy-Rubin ,  Lior Zimet ,  Sergio Kolor

IPC: G06F12/02

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to a plurality of networks of the computer system, which may include packet-switching capabilities. Such non-DRAM transactions may be routed via a virtual channel in some implementations. To facilitate handling of such transactions, the NSM gateway circuit may include dedicated routing storage (e.g., an input buffer for each source agent circuit on each of the plurality of networks and an output buffer for each destination agent circuit on each of the plurality of networks). The NSM gateway circuit may serve as a termination point for non-DRAM transactions within the computer system, allowing network credit for a message included in a non-DRAM transaction to be returned to a source agent circuit prior to delivery to one or more destination agent circuits.

公开(公告)号：US20250103520A1

公开(公告)日：2025-03-27

申请号：US18819755

申请日：2024-08-29

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman ,  Brian P. Lilly ,  John H. Kelm ,  Rohit K. Gupta ,  Sandeep Gupta ,  Anwar Q. Rohillah

IPC: G06F13/16 ,  G06F12/0831

Abstract: A memory controller circuit receives memory access requests from a network of a computer system. Entries are reserved for these requests in a retry queue circuit. An arbitration circuit of the memory controller circuit issues those requests to a tag pipeline circuit that determines whether the received memory access requests hit in a memory cache. As a memory access request passes through the tag pipeline circuit, it may require another pass through this pipeline—for example, if resources such as certain storage circuits needed to complete the memory access request are unavailable (for example a snoop queue circuit). The reservation that has been made in the retry queue circuit thus keeps the request from having to be returned to the network for resubmission to the memory controller circuit if initial processing of the memory access request cannot be completed.

公开(公告)号：US20250103496A1

公开(公告)日：2025-03-27

申请号：US18433118

申请日：2024-02-05

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Amanvir Singh Sidana ,  Sandeep Gupta ,  Tom Greenshtein ,  Vivek Venkatraman

IPC: G06F12/0817 ,  G06F12/0891

Abstract: An apparatus includes a plurality of coherent agents, and a coherence directory that includes directory ways for storing coherency information. The coherence directory may be configured to determine that a cache block that is not currently cached among the coherent agents, is stored in a first coherent agent. The coherence directory may be further configured to, in response to this determination, create a particular entry in a selected one of the directory ways. The coherence directory may also be configured to send, to the first coherent agent, an indicator identifying a directory way that includes the entry. In response to a second coherent agent caching the cache block, the coherence directory may update the entry to include the second coherent agent. The first and second coherent agents may be configured to receive copies of the indicator, and to store their copy in locations associated with the cache block.

公开(公告)号：US20250103477A1

公开(公告)日：2025-03-27

申请号：US18819877

申请日：2024-08-29

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Jurgen M. Schulz ,  Tom Greenshtein ,  Elli Bagelman

IPC: G06F12/02 ,  G06F12/0815 ,  G06F12/12

Abstract: A memory controller circuit manages access to a memory cache circuit and storage circuits. The memory controller receives a memory access request, and attempts to reserve entries in a first set of storage circuits that are needed to process a cache hit prior to determining whether the memory access request hits in the memory cache circuit. This reservation attempt is performed without attempting to reserve other sets of storage circuits that are needed to process other possible outcomes of the memory access request, including a cache miss. If the memory controller circuit has successfully reserved entries in all of the first set of storage circuits, processing of the memory access request may be initiated. Conversely, if the memory controller is unable to reserve an entry in at least one of the first set of storage circuits, processing of the memory access request is inhibited.

公开(公告)号：US11586552B2

公开(公告)日：2023-02-21

申请号：US17320172

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0846 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0862

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

公开(公告)号：US20220365900A1

公开(公告)日：2022-11-17

申请号：US17320082

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Oren Bar ,  Ilya Granovsky

IPC: G06F15/17 ,  G06F15/78 ,  G06F13/40 ,  G06F9/445 ,  G06F9/4401 ,  G06F9/54

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.