公开(公告)号：US20240311319A1

公开(公告)日：2024-09-19

申请号：US18674203

申请日：2024-05-24

Applicant: Apple Inc.

Inventor： Jeffrey E. Gonion ,  Charles E. Tucker ,  Tal Kuzi ,  Richard F. Russo ,  Mridul Agarwal ,  Christopher M. Tsay ,  Gideon N. Levinsky ,  Shih-Chieh Wen ,  Lior Zimet

IPC: G06F13/24 ,  G06F1/26

CPC classification number: G06F13/24 ,  G06F1/26

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

公开(公告)号：US20240184355A1

公开(公告)日：2024-06-06

申请号：US18438665

申请日：2024-02-12

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/3296 ,  G06F1/3206

CPC classification number: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US11836107B2

公开(公告)日：2023-12-05

申请号：US17683396

申请日：2022-03-01

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Lior Zimet ,  Sagi Lahav

IPC: G06F15/78 ,  G06F13/40

CPC classification number: G06F15/7807 ,  G06F13/4013

Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.

公开(公告)号：US20230059725A1

公开(公告)日：2023-02-23

申请号：US17933168

申请日：2022-09-19

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US20220413589A1

公开(公告)日：2022-12-29

申请号：US17899607

申请日：2022-08-30

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brad W. Simeral ,  Lior Zimet

IPC: G06F1/3234 ,  G06F1/3293 ,  G06F1/329

Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.

公开(公告)号：US11467655B1

公开(公告)日：2022-10-11

申请号：US17340940

申请日：2021-06-07

Applicant: Apple Inc.

Inventor： Inder M. Sodhi ,  Achmed R. Zahir ,  Lior Zimet ,  Liran Fishel ,  Omri Flint ,  Ami Schwartzman

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/3206

Abstract: Techniques are disclosed that pertain to synchronizing power states between integrated circuit dies. A system includes an integrated circuit that includes a plurality of integrated circuit dies coupled together. A particular integrated circuit die may include a primary power manager circuit and one or more remaining integrated circuit dies include respective secondary power manager circuits. The primary power manager circuit is configured to issue a transition request to the secondary power manager circuits to transition their integrated circuit dies from a first power state to a second power state. A given secondary power manager circuit is configured to receive the transition request, transition its integrated circuit die to the second power state, and issue an acknowledgement to the primary power manager circuit that its integrated circuit die has been transitioned to the second power state. Techniques are further disclosed relating to managing latency tolerance events within a multi-die integrated circuit.

公开(公告)号：US12265438B2

公开(公告)日：2025-04-01

申请号：US18175900

申请日：2023-02-28

Applicant: Apple Inc.

Inventor： Tzach Zemer ,  Lior Zimet ,  Sagi Lahav

IPC: G06F1/3206 ,  G06F1/08 ,  G06F1/3234 ,  H04W52/02

Abstract: A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.

公开(公告)号：US20250094330A1

公开(公告)日：2025-03-20

申请号：US18404822

申请日：2024-01-04

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Lital Levy-Rubin ,  Lior Zimet ,  Sergio Kolor

IPC: G06F12/02

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to a plurality of networks of the computer system, which may include packet-switching capabilities. Such non-DRAM transactions may be routed via a virtual channel in some implementations. To facilitate handling of such transactions, the NSM gateway circuit may include dedicated routing storage (e.g., an input buffer for each source agent circuit on each of the plurality of networks and an output buffer for each destination agent circuit on each of the plurality of networks). The NSM gateway circuit may serve as a termination point for non-DRAM transactions within the computer system, allowing network credit for a message included in a non-DRAM transaction to be returned to a source agent circuit prior to delivery to one or more destination agent circuits.

公开(公告)号：US12236130B2

公开(公告)日：2025-02-25

申请号：US18318672

申请日：2023-05-16

Applicant: Apple Inc.

Inventor： Steven Fishwick ,  Lior Zimet ,  Harshavardhan Kaushikkar

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0871 ,  G06F12/0882 ,  G06F12/1018 ,  G06F12/1045 ,  G06F13/16

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

公开(公告)号：US20240411716A1

公开(公告)日：2024-12-12

申请号：US18811861

申请日：2024-08-22

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Lior Zimet ,  Sagi Lahav

IPC: G06F15/78 ,  G06F13/40

Abstract: An electronic device includes circuitry and a plurality of ports. The plurality of ports includes an input port and an output port, configured to communicate data units with one or more other devices across a fabric of a System on a Chip (SoC), the data units include N data bits, N being an integer larger than 1. The circuitry is configured to receive an input data unit via the input port, to make a random decision of whether to invert the N data bits in the input data unit, to produce an output data unit by retaining or inverting the N data bits of the input data unit based on the random decision, and to send the output data unit via the output port.