公开(公告)号：US20220365881A1

公开(公告)日：2022-11-17

申请号：US17320172

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/0891 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/02 ,  G06F12/06

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

公开(公告)号：US20250097167A1

公开(公告)日：2025-03-20

申请号：US18404837

申请日：2024-01-04

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Lital Levy-Rubin ,  Lior Zimet ,  Sergio Kolor

IPC: H04L49/253 ,  H04L49/90

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to first and second networks of the computer system. The NSM gateway circuit may route, for example, a message for a non-DRAM transaction from a source agent circuit coupled to the first network but not the second network to a destination agent circuit coupled to the second network but not the first network, and vice-versa. The NSM gateway circuit can also route messages for non-DRAM transactions between source and destination agent circuits both located on the same network. Still further, the NSM gateway circuit can route broadcast (i.e., one-to-many) transactions as well as network element configuration requests. In some implementations, a computer system may have multiple NSM gateway circuits, each assigned to handle non-DRAM transactions from an assigned set of agent circuits.

公开(公告)号：US20250044844A1

公开(公告)日：2025-02-06

申请号：US18365783

申请日：2023-08-04

Applicant: Apple Inc.

Inventor： Doron Rajwan ,  Alexander Gendler ,  Daniel U. Becker ,  Saher Odeh ,  Ilya Granovsky ,  Lior Zimet

IPC: G06F1/26

Abstract: Techniques are disclosed relating to selective rate limiting and reducing clock frequency of fabric circuitry in response to certain power management events. Disclosed techniques may advantageously allow power management circuitry to reduce or avoid negative impacts of power events by reducing the clock frequency of a communication fabric while using rate limiting of relatively lower-priority traffic to reduce impacts of the frequency reduction on high-priority traffic. For example, rate limiting of lower-quality-of-service virtual channels may continue after recovery of the clock frequency until higher-quality-of-service virtual channels have recovered from the frequency reduction.

公开(公告)号：US12007901B2

公开(公告)日：2024-06-11

申请号：US18171617

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/08 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0846 ,  G06F12/0862 ,  G06F12/0891

CPC classification number: G06F12/0891 ,  G06F12/0238 ,  G06F12/0646 ,  G06F12/0846 ,  G06F12/0862

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

公开(公告)号：US20230259459A1

公开(公告)日：2023-08-17

申请号：US18171617

申请日：2023-02-20

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Tom Greenshtein

IPC: G06F12/0891 ,  G06F12/0846 ,  G06F12/06 ,  G06F12/02 ,  G06F12/0862

CPC classification number: G06F12/0891 ,  G06F12/0846 ,  G06F12/0646 ,  G06F12/0238 ,  G06F12/0862

Abstract: An apparatus includes a cache memory circuit configured to store a cache lines, and a cache controller circuit. The cache controller circuit is configured to receive a read request to an address associated with a portion of a cache line. In response to an indication that the portion of the cache line currently has at least a first sub-portion that is invalid and at least a second sub-portion that is modified relative to a version in a memory, the cache controller circuit is further configured to fetch values corresponding to the address from the memory, to generate an updated version of the portion of the cache line by using the fetched values to update the first sub-portion, but not the second sub-portion, of the portion of the cache line, and to generate a response to the read request that includes the updated version of the portion of the cache line.

公开(公告)号：US11693472B2

公开(公告)日：2023-07-04

申请号：US17676668

申请日：2022-02-21

Applicant: Apple Inc.

Inventor： Ilya Granovsky ,  Doron Rajwan ,  Tal Kuzi ,  Nir Leshem ,  Lior Zimet

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/324 ,  G06F1/3206

Abstract: Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Certain techniques include the implementation of rate control circuits to control a clock rate for circuits associated with a communication fabric in an integrated circuit. The clock rate may be reduced based trigger signals received from power delivery trigger circuits coupled to the integrated circuit and voltage regulators providing power to the integrated circuit. Additional techniques may include the use of rate limiter circuits in a memory pipeline.

公开(公告)号：US11609878B2

公开(公告)日：2023-03-21

申请号：US17320082

申请日：2021-05-13

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Oren Bar ,  Ilya Granovsky

IPC: G06F15/17 ,  G06F15/78 ,  G06F9/54 ,  G06F9/445 ,  G06F9/4401 ,  G06F13/40

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.