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    Flexible System Integration to Improve Thermal Properties
    11.
    发明申请
    Flexible System Integration to Improve Thermal Properties 审中-公开

    公开(公告)号：US20180076112A1

    公开(公告)日：2018-03-15

    申请号：US15263632

    申请日：2016-09-13

    Applicant: Apple Inc.

    Inventor： Sanjay Dabral

    IPC: H01L23/373 ,  H01L23/538 ,  H01L23/00

    Abstract: In an embodiment, an interposer includes multiple integrated circuits coupled thereto. The integrated circuits may include processors and non-processor functionality that may have previously been integrated with the processors on an SOC. By separating the functionality into multiple integrated circuits, the integrated circuits may be arranged on the interposer to spread out the potentially high power ICs and lower power ICs, interleaving them. In other embodiments, instances of the integrated circuits (e.g. processors) from different manufacturing process conditions may be selected to allow a mix of high performance, high power density integrated circuits and lower performance, low power density integrated circuits. In an embodiment, a phase change material may be in contact with the integrated circuits, providing a local reservoir to absorb heat. In an embodiment, a battery or display components may increase thermal mass and allow longer optimal performance state operation.

    Optimized ESD clamp circuitry
    13.
    发明授权
    Optimized ESD clamp circuitry 有权

    公开(公告)号：US09679891B2

    公开(公告)日：2017-06-13

    申请号：US14220293

    申请日：2014-03-20

    Applicant: Apple Inc.

    Inventor： Sanjay Dabral ,  Xiaofeng Fan ,  Geertjan Joordens

    IPC: H01L27/02 ,  H02H3/20 ,  H02H3/22 ,  H02H9/04

    CPC classification number: H01L27/0285 ,  H02H3/20 ,  H02H3/22 ,  H02H9/046

    Abstract: ESD protection circuitry is disclosed. In one embodiment, an integrated circuit includes first and second sensor circuits. The first sensor circuit has a first resistive-capacitive (RC) time constant, while the second sensor circuit has a second RC time constant. The RC time constant of the first sensor circuit is at least one order of magnitude greater than that of the second sensor circuit. A first clamp transistor is coupled to and configured to be activated by the first sensor circuit responsive to the latter detecting an ESD event. A second clamp transistor is coupled to and configured to be activated by the second sensor circuit responsive to the latter detecting the ESD event.

    ESD Protection for Advanced CMOS Processes
    14.
    发明申请
    ESD Protection for Advanced CMOS Processes 审中-公开
    高级CMOS工艺的ESD保护

    公开(公告)号：US20150380397A1

    公开(公告)日：2015-12-31

    申请号：US14501773

    申请日：2014-09-30

    Applicant: Apple Inc.

    Inventor： Sanjay Dabral ,  Xiaofeng Fan

    IPC: H01L27/02

    CPC classification number: H01L27/0266 ,  H01L27/0255

    Abstract: Various embodiments of ESD protection circuits and methods for operating the same are disclosed. In one embodiment, one or more driver circuits are protected by a first ESD protection circuit configured to activate and discharge current responsive to an ESD event. The driver circuit may include a pull-up transistor and a pull-down transistor each coupled to drive an output node. A second ESD protection circuit may be associated with and dedicated to the pull-up transistor in the driver circuit.

    Abstract translation: 公开了ESD保护电路的各种实施例及其操作方法。 在一个实施例中，一个或多个驱动器电路由被配置为响应于ESD事件激活和放电电流的第一ESD保护电路来保护。 驱动器电路可以包括每个耦合以驱动输出节点的上拉晶体管和下拉晶体管。 第二ESD保护电路可以与驱动器电路中的上拉晶体管相关联并且专用于上拉晶体管。

    SYSTEMS AND METHODS FOR INTERCONNECTING DIES
    16.
    发明申请
    SYSTEMS AND METHODS FOR INTERCONNECTING DIES 有权

    公开(公告)号：US20250157940A1

    公开(公告)日：2025-05-15

    申请号：US19021018

    申请日：2025-01-14

    Applicant: Apple Inc.

    Inventor： Sanjay Dabral ,  Jun Zhai

    IPC: H01L23/538 ,  H01L21/66 ,  H01L23/00 ,  H01L23/488 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L25/18

    Abstract: Stitched die structures, and methods for interconnecting die are described. In an embodiment, a stitched die structure includes a semiconductor substrate that includes a first die area of a first die and a second die area of a second die separate from the first die area. A back-end-of-the-line (BEOL) build-up structure spans over the first die area and the second die area, and includes a first metallic seal directly over a first peripheral area of the first die area, a second metallic seal directly over a second peripheral area of the second die area, and a die-to-die routing extending through the first metallic seal and the second metallic seal to electrically connect the first die to the second die.

    Scalable large system based on organic interconnect
    19.
    发明授权
    Scalable large system based on organic interconnect 有权

    公开(公告)号：US12237269B2

    公开(公告)日：2025-02-25

    申请号：US17655157

    申请日：2022-03-16

    Applicant: Apple Inc.

    Inventor： Sanjay Dabral ,  Ravindranath T. Kollipara

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

    Abstract: Multi-chip modules and methods of fabrication are described. The MCM may include a plurality of dies in which die-to-die routing can be partitioned within multiple metal routing layers for shorter die-to-die routings, while longer die-to-die routing can be routed primarily in a single metal routing layer. The plurality of dies may also be arranged in a spaced apart relationship to accommodate additional wiring area, while preserving direct routing areas for the longer die-to-die routing.

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