公开(公告)号：US20240085968A1

公开(公告)日：2024-03-14

申请号：US18175900

申请日：2023-02-28

Applicant: Apple Inc.

Inventor： Tzach Zemer ,  Lior Zimet ,  Sagi Lahav

IPC: G06F1/3206 ,  G06F1/08 ,  G06F1/3234 ,  H04W52/02

CPC classification number: G06F1/3206 ,  G06F1/08 ,  G06F1/3234 ,  H04W52/02

Abstract: A system for a given device may include a plurality of systems on a chip (SOCs). Each SOC may include an interface circuit and a bridge circuit for communicating with other SOCs. The interface circuit of an SOC may include a plurality of communication devices to transfer data packets from/to the SOC to the other SOCs. The bridge circuit may provide various control functions for the interface circuit. An indication may be generated when the system enters an idle mode. In response, the bridge circuit may generate signal(s) to cause some of the communication devices of the interface circuit into a low power state. The interface circuit may obtain the signal(s) and accordingly transition some of the communication devices to the low power state.

公开(公告)号：US20230239252A1

公开(公告)日：2023-07-27

申请号：US17868495

申请日：2022-07-19

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Lior Zimet ,  Opher D. KAHN ,  Eran Tamari ,  Tzach Zemer ,  Per H. Hammarlund

IPC: H04L49/25 ,  H04L47/10

CPC classification number: H04L49/25 ,  H04L47/39

Abstract: In an embodiment, a system includes a plurality of integrated circuits have subsets of a plurality of agents. The plurality of integrated circuits may have network segments implemented wholly (e.g., entirely) within the respective integrated circuits and may have segment to segment (S2S) network interface circuits to couple to other network segments of a plurality of network segment forming a network among the plurality of agents.

公开(公告)号：US20230214350A1

公开(公告)日：2023-07-06

申请号：US18174985

申请日：2023-02-27

Applicant: Apple Inc.

Inventor： Dany Davidov ,  Misbah Ramadan ,  Itamar Rozen ,  Tzach Zemer

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F9/30083 ,  G06F13/4022

Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

公开(公告)号：US11675722B2

公开(公告)日：2023-06-13

申请号：US17337805

申请日：2021-06-03

Applicant: Apple Inc.

Inventor： Sergio Kolor ,  Sergio V. Tota ,  Tzach Zemer ,  Sagi Lahav ,  Jonathan M. Redshaw ,  Per H. Hammarlund ,  Eran Tamari ,  James Vash ,  Gaurav Garg ,  Lior Zimet ,  Harshavardhan Kaushikkar ,  Steven Fishwick ,  Steven R. Hutsell ,  Shawn M. Fukami

IPC: G06F13/40 ,  G06F15/173

CPC classification number: G06F13/4027 ,  G06F13/4022 ,  G06F15/17375 ,  G06F15/17381

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a plurality of agents and a plurality of network switches coupled to the plurality of agents. The plurality of network switches are interconnected to form a plurality of physical and logically independent networks. A first network of the plurality of physically and logically independent networks is constructed according to a first topology and a second network of the plurality of physically and logically independent networks is constructed according to a second topology that is different from the first topology. For example, the first topology may a ring topology and the second topology may be a mesh topology. In an embodiment, coherency may be enforced on the first network and the second network may be a relaxed order network.

公开(公告)号：US20220365579A1

公开(公告)日：2022-11-17

申请号：US17318670

申请日：2021-05-12

Applicant: Apple Inc.

Inventor： Dany Davidov ,  Misbah Ramadan ,  Itamar Rozen ,  Tzach Zemer

IPC: G06F1/3203 ,  G06F13/40 ,  G06F13/36 ,  G06F1/18

Abstract: A system includes a plurality of systems-on-a-chip (SoCs), connected by a network. The plurality of SoCs and the network are configured to operate as a single logical computing system. The plurality of SoCs may be configured to exchange local power information indicative of network activity occurring on their respective portions of the network. A given one of the plurality of SoCs may be configured to determine that a local condition for placing the respective portion of the network corresponding to the given SoC into a reduced power mode has been satisfied. The given SoC may be further configured to place the respective portion of the network into the reduced power mode in response to determining that a global condition for the reduced power mode is satisfied. The global condition may be assessed based upon current local power information for remaining ones of the plurality of SoCs.

公开(公告)号：US09641158B2

公开(公告)日：2017-05-02

申请号：US14831708

申请日：2015-08-20

Applicant: Apple Inc.

Inventor： Tzach Zemer ,  Joseph J. Cheng

IPC: H04R3/04 ,  H03G5/00 ,  H03H17/06

CPC classification number: H03H17/0664 ,  H03H17/0226 ,  H04R3/00 ,  H04R3/04 ,  H04R2410/00

Abstract: Systems, apparatuses, and methods for implementing a low power decimator. A decimator may receive a plurality of input samples from a digital microphone. The decimator may include one or more coefficient tables for storing values combining two or more filter coefficients for filtering the received samples. The decimator may utilize a concatenation of multiple samples to perform a lookup of a corresponding coefficient table. The coefficient tables may store only the necessary non-redundant values for all coefficient combinations which can be applied to the multiple samples. The result of the lookup of the coefficient table may have its sign inverted or be zeroed based on the values of the multiple samples.