公开(公告)号：US20250071415A1

公开(公告)日：2025-02-27

申请号：US18943384

申请日：2024-11-11

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Chaminda N. Vidanagamachchi ,  Yohan Rajan ,  Anselm Grundhoefer

IPC: H04N23/65 ,  G06V10/10 ,  G06V10/147 ,  G06V10/22 ,  G06V10/82 ,  G06V20/52 ,  G06V20/58 ,  G08B13/196 ,  H04N7/18 ,  H04N23/45 ,  H04N23/61 ,  H04N23/667

Abstract: An apparatus includes a primary camera sensor configured to capture images having a first resolution, a primary processing circuit configured to process images captured by the primary camera sensor, a secondary camera sensor configured to capture images having a second resolution, and a secondary processing circuit configured to process images captured by the secondary camera sensor. In response to a determination that a particular object of interest is included in a particular image, the secondary processing circuit may be further configured to cause the primary processing circuit and the primary camera sensor to exit a reduced power mode. The primary camera sensor may be further configured, in response to the exiting, to capture a different image. The primary processing circuit may also be configured to process the different image to validate the particular object of interest.

公开(公告)号：US12135993B2

公开(公告)日：2024-11-05

申请号：US18321919

申请日：2023-05-23

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Yohan Rajan ,  Chaminda Nalaka Vidanagamachchi ,  Anthony Ghannoum

IPC: G06F9/50 ,  G06F9/30

Abstract: In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.

公开(公告)号：US11693699B2

公开(公告)日：2023-07-04

申请号：US16919930

申请日：2020-07-02

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Yohan Rajan ,  Chaminda Nalaka Vidanagamachchi ,  Anthony Ghannoum

IPC: G06F9/50 ,  G06F9/30

CPC classification number: G06F9/5016 ,  G06F9/3004 ,  G06F9/5044

Abstract: In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.

公开(公告)号：US11593628B2

公开(公告)日：2023-02-28

申请号：US16810675

申请日：2020-03-05

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Waleed Abdulla ,  Chaminda N. Vidanagamachchi ,  Yohan Rajan

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

公开(公告)号：US11308685B2

公开(公告)日：2022-04-19

申请号：US17028887

申请日：2020-09-22

Applicant: Apple Inc.

Inventor： Siddharth S. Hazra ,  William J. Dobbie ,  Moinul H. Khan ,  Yanli Zhang ,  Yohan Rajan ,  Arthur Y. Zhang

IPC: G06T15/20 ,  G06T7/73 ,  G06F3/01 ,  G06T19/00

Abstract: Various implementations disclosed herein include devices, systems, and methods that dynamically-size zones used in foveated rendering of content that includes text. In some implementations, this involves adjusting the size of a first zone, e.g., a foveated gaze zone (FGZ), based on the apparent size of text from a viewpoint. For example, a FGZ may be increased or decreased in width, height, diameter, or other size attribute based on determining an angle subtended by one or more individual glyphs of the text from the viewpoint. Various implementations disclosed herein include devices, systems, and methods that select a text-rendering algorithm based on a relationship between (a) the rendering resolution of a portion of an image corresponding to a part of a glyph and (b) the size that the part of the glyph will occupy in the image.

公开(公告)号：US20220004236A1

公开(公告)日：2022-01-06

申请号：US16919908

申请日：2020-07-02

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Yohan Rajan ,  Chaminda Nalaka Vidanagamachchi

IPC: G06F1/26 ,  G06F9/30

Abstract: In an embodiment, a local memory that is dedicated to one or more hardware accelerators is divided into a plurality of independently powerable sections. That is, one or more of the sections may be powered on while other ones of the plurality of sections are powered off. The hardware accelerators receive instruction words from one or more central processing units (CPUs). The instruction words may include a field that specifies an amount of the memory that is used when processing the first instruction word, and the power control circuit may be configured to power a subset of the plurality of sections to provide sufficient memory for the instruction word based on the field, while one or more of the plurality of sections are powered off.

公开(公告)号：US20210279557A1

公开(公告)日：2021-09-09

申请号：US16810675

申请日：2020-03-05

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Waleed Abdulla ,  Chaminda N. Vidanagamachchi ,  Yohan Rajan

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

公开(公告)号：US20250130482A1

公开(公告)日：2025-04-24

申请号：US19002384

申请日：2024-12-26

Applicant: Apple Inc.

Inventor： Justin J. Schwab ,  Nathanael D. Parkhill ,  Andrew McMahon ,  Jae Lee ,  Jerome Tu ,  DK Kalinowski ,  Nalaka Vidanagamachchi ,  Yohan Rajan ,  Cam Harder ,  Yoshikazu Shinohara

IPC: G03B17/18 ,  G02B5/00 ,  G02B13/00 ,  G02B27/01 ,  G02B27/09 ,  G03B30/00 ,  G11B27/34 ,  H04N5/765 ,  H04N5/77 ,  H04N23/54 ,  H04N23/56 ,  H04N23/57 ,  H04N23/60 ,  H04N23/61 ,  H04N23/63 ,  H04N23/80

Abstract: Recording indicators for devices with cameras that provide protection from tampering so that the recording indicators cannot be easily disabled or masked. Recording indicators that are external to the camera lens and that emit visible light in an encrypted pattern are described. The device may process captured frames to detect the encrypted pattern; if the encrypted pattern cannot be detected, recording is disabled. In addition, modular accessories are described that the user has to attach to the device to enable recording; the presence of the modular attachment indicates to persons in the environment that they may be being recorded.

公开(公告)号：US12050987B2

公开(公告)日：2024-07-30

申请号：US18114169

申请日：2023-02-24

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Waleed Abdulla ,  Chaminda N Vidanagamachchi ,  Yohan Rajan

IPC: G06N3/063 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06N3/04 ,  G06N3/08

Abstract: Embodiments relate to an electronic device that includes a neural processor having multiple neural engine circuits that operate in multiple modes of different bit width. A neural engine circuit may include a first multiply circuit and a second multiply circuit. The first and second multiply circuits may be combined to work as a part of a combined computation circuit. In a first mode, the first multiply circuit generates first output data of a first bit width by multiplying first input data with a first kernel coefficient. The second multiply circuit generates second output data of the first bit width by multiplying second input data with a second kernel coefficient. In a second mode, the combined computation circuit generates third output data of a second bit width by multiplying third input data with a third kernel coefficient.

公开(公告)号：US11385693B2

公开(公告)日：2022-07-12

申请号：US16919908

申请日：2020-07-02

Applicant: Apple Inc.

Inventor： Paolo Di Febbo ,  Yohan Rajan ,  Chaminda Nalaka Vidanagamachchi

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/30 ,  G06F1/3203

Abstract: In an embodiment, a local memory that is dedicated to one or more hardware accelerators is divided into a plurality of independently powerable sections. That is, one or more of the sections may be powered on while other ones of the plurality of sections are powered off. The hardware accelerators receive instruction words from one or more central processing units (CPUs). The instruction words may include a field that specifies an amount of the memory that is used when processing the first instruction word, and the power control circuit may be configured to power a subset of the plurality of sections to provide sufficient memory for the instruction word based on the field, while one or more of the plurality of sections are powered off.