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    Acceleration of In-Memory-Compute Arrays
    3.
    发明申请
    Acceleration of In-Memory-Compute Arrays 有权

    公开(公告)号：US20230059200A1

    公开(公告)日：2023-02-23

    申请号：US17406817

    申请日：2021-08-19

    Applicant: Apple Inc.

    Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

    IPC: G11C7/22 ,  G11C7/10 ,  H03M1/82

    Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

    Acceleration of in-memory-compute arrays
    4.
    发明授权
    Acceleration of in-memory-compute arrays 有权

    公开(公告)号：US12230361B2

    公开(公告)日：2025-02-18

    申请号：US18346565

    申请日：2023-07-03

    Applicant: Apple Inc.

    Inventor： Paolo Di Febbo ,  Mohamed H. Abu-Rahma ,  Jelam K. Parekh ,  Yildiz Sinangil ,  Mohammad Ghasemzadeh ,  Anthony Ghannoum ,  Chaminda N. Vidanagamachchi

    IPC: G11C8/00 ,  G11C7/10 ,  G11C7/22 ,  H03M1/82

    Abstract: An apparatus includes an in-memory compute circuit that includes a memory circuit configured to generate a set of products by combining received input values with respective weight values stored in rows of the memory circuit, and to combine the set of products to generate an accumulated output value. The in-memory compute circuit may further include a control circuit and a plurality of routing circuits, including a first routing circuit coupled to a first set of rows of the memory circuit. The control circuit may be configured to cause the first routing circuit to route groups of input values to different ones of the first set of rows over a plurality of clock cycles, and the memory circuit to generate, on a clock cycle following the plurality of clock cycles, a particular accumulated output value that is computed based on the routed groups of input values.

    Display tracking systems and methods
    6.
    发明授权
    Display tracking systems and methods 有权

    公开(公告)号：US11954885B2

    公开(公告)日：2024-04-09

    申请号：US17476312

    申请日：2021-09-15

    Applicant: Apple Inc.

    Inventor： Paolo Di Febbo ,  Anthony Ghannoum ,  Michele Stoppa ,  Kiranjit Dhaliwal

    IPC: G06T7/73 ,  G01S5/02 ,  G01S5/16 ,  G06F3/14 ,  G06T13/00 ,  H04N23/65 ,  H04N23/66

    CPC classification number: G06T7/74 ,  G06F3/14 ,  G06T13/00 ,  H04N23/651 ,  H04N23/66 ,  G01S5/02585 ,  G01S5/16

    Abstract: A tracked device may be used in an extended reality system in coordination with a tracking device. The tracked device may be ordinarily difficult to track, for example due to changing appearances or relatively small surface areas of unchanging features, as may be the case with an electronic device with a relatively large display surrounded by a thin physical outer boundary. In these cases, the tracked device may periodically present an image to the tracking device that the tracking device stores as an indication to permit tracking of a known, unchanging feature despite the image not being presented continuously on the display of the tracked device. The image may include a static image, designated tracking data overlaid on an image frame otherwise scheduled for presentation, or extracted image features from the image frame otherwise scheduled for presentation. Additional power saving methods and known marker generation methods are also described.

    CROSSBAR CIRCUIT FOR UNALIGNED MEMORY ACCESS IN NEURAL NETWORK PROCESSOR
    8.
    发明申请
    CROSSBAR CIRCUIT FOR UNALIGNED MEMORY ACCESS IN NEURAL NETWORK PROCESSOR 有权

    公开(公告)号：US20230135306A1

    公开(公告)日：2023-05-04

    申请号：US17518059

    申请日：2021-11-03

    Applicant: Apple Inc.

    Inventor： Paolo Di Febbo ,  Anthony Ghannoum

    IPC: G06N3/063 ,  G11C7/10 ,  G11C11/40

    Abstract: Embodiments of the present disclosure relate to an unaligned memory access in a neural processor circuit. The neural processor circuit includes a crossbar circuit and a neural engine circuit coupled to the crossbar circuit. During each operating cycle of the neural processor circuit, the crossbar circuit receives a portion of input data, and re-aligns or bypasses the portion of input data. The neural engine circuit receives at least a portion of the re-aligned or bypassed portion of the input data, and performs a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.

    Hybrid memory in a dynamically power gated hardware accelerator
    10.
    发明授权
    Hybrid memory in a dynamically power gated hardware accelerator 有权

    公开(公告)号：US12135993B2

    公开(公告)日：2024-11-05

    申请号：US18321919

    申请日：2023-05-23

    Applicant: Apple Inc.

    Inventor： Paolo Di Febbo ,  Yohan Rajan ,  Chaminda Nalaka Vidanagamachchi ,  Anthony Ghannoum

    IPC: G06F9/50 ,  G06F9/30

    Abstract: In an embodiment, a local memory dedicated to one or more hardware accelerators in a system may include at least two portions: a volatile portion and a non-volatile portion. Data that is reused from iteration to iteration of the hardware accelerator (e.g. constants, instruction words, etc.) may be stored in the non-volatile portion. Data that varies from iteration to iteration may be stored in the volatile portion. Both the local memory and the hardware accelerators may be powered down between iterations, saving power. The non-volatile portion need only be initialized at a first iteration, allowing the amount of time that the hardware accelerators and the local memory are powered up to be lessened for subsequent iterations since the reused data need not be reloaded in the subsequent iterations.

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