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    INTEGRATED METALLIZATION FOR DISPLAYS
    11.
    发明公开
    INTEGRATED METALLIZATION FOR DISPLAYS 失效
    综合金属化用于显示器

    公开(公告)号：EP0979524A1

    公开(公告)日：2000-02-16

    申请号：EP98914286.4

    申请日：1998-03-24

    Applicant: Candescent Technologies Corporation

    Inventor： LEARN, Arthur, J. ,  HAVEN, Duane, A.

    IPC: H01J5/00 ,  H01J17/49

    CPC classification number: H01J31/127 ,  H01J29/90 ,  H01J2329/90

    Abstract: A flat-panel display (100) including a substrate (102), a viewing screen (104), a non-conductive ring (106), many row conductive electrodes (120), conductive pads (122) and column buses (130). The ring vacuum-seals a cavity (108) between the substrate and the viewing screen. Coupled to one surface of the substrate, the row conductive electrodes have a conductivity that is higher than the conductive pads. Each pad is connected to one row electrode, and each pad extends through the ring to allow electrical coupling to its corresponding row electrode from outside the cavity while vacuum is maintained inside the cavity. The row electrodes are substantially parallel to each other, and are substantially perpendicular to the column buses. The conductive electrodes are protected from exposure to the ring. In one embodiment, the ring is a frit seal (106), the row conductive electrodes are made of aluminum, and the column buses and the pads are made of chromium.

    FLAT PANEL DISPLAY WITH REDUCED ELECTRON SCATTERING EFFECTS
    13.
    发明授权
    FLAT PANEL DISPLAY WITH REDUCED ELECTRON SCATTERING EFFECTS 失效
    与还原的电子TRUST影响平板显示器

    公开(公告)号：EP0862785B1

    公开(公告)日：2002-07-03

    申请号：EP96942041.3

    申请日：1996-11-20

    Applicant: Candescent Technologies Corporation

    Inventor： SPINDT, Christopher, J. ,  FIELD, John, E. ,  HAVEN, Duane, A.

    IPC: H01J31/12 ,  H01J29/02

    CPC classification number: H01J29/327 ,  H01J9/242 ,  H01J29/085 ,  H01J29/864 ,  H01J31/127 ,  H01J2329/8625 ,  H01J2329/863 ,  H01J2329/8665

    Abstract: A flat panel display is disclosed which includes a faceplate with a faceplate interior side, and a backplate including a backplate interior side in an opposing relationship to the faceplate interior side. Side walls are positioned between the faceplate and the backplate. The side walls, faceplate and backplate form an enclosed sealed envelope. A plurality of phosphor subpixels are positioned at the faceplate interior side. A plurality of field emitters are positioned at the backplate interior side. The field emitters emit electrons which strike corresponding phosphor subpixels. A plurality of scattering shields surround each phosphor subpixel and define a subpixel volume. The scattering shields reduce the number of scattered electrons exiting from their corresponding subpixel volume. This reduces the number of scattered electrons from charging internal insulating surfaces in the envelope, as well as striking the non-corresponding phosphor subpixels.

    MULTI-LAYER RESISTOR FOR AN EMITTING DEVICE
    14.
    发明公开
    MULTI-LAYER RESISTOR FOR AN EMITTING DEVICE 失效
    用于发射装置的多层电阻器

    公开(公告)号：EP0993679A1

    公开(公告)日：2000-04-19

    申请号：EP98930256.7

    申请日：1998-06-19

    Applicant: Candescent Technologies Corporation

    Inventor： KNALL, Johan, N. ,  HAVEN, Duane, A. ,  RAMANI, Swayambu

    IPC: H01J1/62

    CPC classification number: H01J3/022 ,  H01J2201/319 ,  H01J2329/00

    Abstract: An electron-emitting device employs a multi-layer resistor (46). A lower layer (48) of the resistor overlies an emitter electrode (42). An electron-emissive element (54) overlies an upper layer (50) of the resistor. The two resistive layers are of different chemical composition. The upper resistive layer is typically formed with cermet. The lower resistive layer is typically formed with a silicon-carbon compound. In fabricating the device, the upper resistive layer normally serves as an etch stop for protecting the lower resistive layer and the emitter electrode during the etch of an overlying dielectric layer (52) to form an opening (56) in which the electron-emissive element is later provided.

    Abstract translation: 电子发射器件采用多层电阻器（46）。 电阻器的下层（48）覆盖发射电极（42）。 电子发射元件（54）覆盖电阻器的上层（50）。 这两个电阻层具有不同的化学组成。 上电阻层通常由金属陶瓷形成。 下电阻层通常由硅 - 碳化合物形成。 在制造器件时，上电阻层通常用作蚀刻停止层，用于在上覆电介质层（52）的蚀刻期间保护下电阻层和发射电极以形成开口（56），其中电子发射元件 稍后提供。

    METHOD OF FABRICATING AN ELECTRON-EMITTING DEVICE
    15.
    发明公开
    METHOD OF FABRICATING AN ELECTRON-EMITTING DEVICE 失效
    方法用于制造电子发射装置

    公开(公告)号：EP0909347A1

    公开(公告)日：1999-04-21

    申请号：EP97927841.0

    申请日：1997-06-05

    Applicant: Candescent Technologies Corporation

    Inventor： HAVEN, Duane, A. ,  SLUZKY, Esther ,  MACAULAY, John, M.

    IPC: C25D13 ,  H01J9

    CPC classification number: H01J9/025

    Abstract: A method for creating a solid layer (36A or 52A) through which openings (38 or 54) extend entails subjecting particles (30) suspended in a fluid (26) to an electric field (EA) to cause a number of the particles to move towards, and accumulate over, a structure placed in the fluid. The structure, including the so-accumulated particles, is removed from the fluid. Solid material is deposited over the structure at least in the space between the so-accumulated particles. The particles, including any overlying material (36B or 52B), are removed. The remaining solid material forms the solid layer through which openings extend at the locations of the so-removed particles. The structure is typically a partially finished electron-emitting device. The solid layer is then typically either a gate layer for the electron-emitting device or a layer used in forming the gate layer.

    GATED ELECTRON EMISSION DEVICE AND METHOD OF FABRICATION THEREOF
    16.
    发明公开
    GATED ELECTRON EMISSION DEVICE AND METHOD OF FABRICATION THEREOF 失效
    GRID控制的电子发射装置及其制造方法

    公开(公告)号：EP1018131A1

    公开(公告)日：2000-07-12

    申请号：EP97926809.1

    申请日：1997-06-05

    Applicant: Candescent Technologies Corporation

    Inventor： HAVEN, Duane, A. ,  LUDWIG, Paul, N. ,  SPINDT, Christopher, J. ,  DOBKIN, Daniel, M.

    IPC: H01J1/30

    CPC classification number: H01J9/025 ,  H01J2329/00

    Abstract: A gated electron-emitter is fabricated by a process in which particles (26) are deposited over an insulating layer (24). Gate material is provided over the insulating layer in the space between the particles after which the particles and any overlying material are removed. The remaining gate material forms a gate layer (28A or 48A) through which gate openings (30 or 50) extend at the locations of the removed particles. When the gate material deposition is performed so that part of the gate material extends into the spaces below the particles, the gate openings are beveled. The insulating layer is etched through the gate openings to form dielectric openings (32 or 52). Electron-emissive elements (36A or 56A) are formed in the dielectric openings. This typically involves introducing emitter material through the gate openings into the dielectric openings and using a lift-off layer (34), or an electrochemical technique, to remove excess emitter material.

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