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公开(公告)号：DE3527284A1
公开(公告)日：1986-02-13
申请号：DE3527284
申请日：1985-07-30
Applicant: CANON KK
Inventor： NAKAGAWA KATSUMI , KOMATSU TOSHIYUKI , SEITO SHINICHI , KURODA YASUO , HATANAKA KATSUNORI
Abstract: A matrix circuit has a plurality of blocks each including a plurality of semiconductor unit elements, the semiconductor unit elements of each block being adapted to be impressed with a predetermined voltage at the same time, each unit element becoming active when impressed with the predetermined voltage, and a drive device for impressing the predetermined voltage to the plurality of blocks sequentially. The matrix circuit includes a first selective device for selecting either ground or a desired other than ground voltage, and a second selective device for selecting one of the output of the drive device and the output of the first selective device whereby the output of the second selective device renders active the plurality of unit elements of each block.
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公开(公告)号：GB2151874B
公开(公告)日：1987-05-28
申请号：GB8429542
申请日：1984-11-22
Applicant: CANON KK
Inventor： NAKAGAWA KATSUMI , HATANAKA KATSUNORI , SEITOH SHINICHI , KURODA YASUO , KOMATSU TOSHIYUKI
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公开(公告)号：FR2568709A1
公开(公告)日：1986-02-07
申请号：FR8511629
申请日：1985-07-30
Applicant: CANON KK
Inventor： NAKAGAWA KATSUMI , KOMATSU TOSHIYUKI , SEITO SHINICHI , KURODA YASUO , HATANAKA KATSUNORI
Abstract: A matrix circuit has a plurality of blocks each including a plurality of semiconductor unit elements, the semiconductor unit elements of each block being adapted to be impressed with a predetermined voltage at the same time, each unit element becoming active when impressed with the predetermined voltage, and a drive device for impressing the predetermined voltage to the plurality of blocks sequentially. The matrix circuit includes a first selective device for selecting either ground or a desired other than ground voltage, and a second selective device for selecting one of the output of the drive device and the output of the first selective device whereby the output of the second selective device renders active the plurality of unit elements of each block.
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公开(公告)号：DE3442605A1
公开(公告)日：1985-05-30
申请号：DE3442605
申请日：1984-11-22
Applicant: CANON KK
Inventor： NAKAGAWA KATSUMI , HATANAKA KATSUNORI , SEITOH SHINICHI , KURODA YASUO , KOMATSU TOSHIYUKI
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15.发明专利
公开(公告)号：JPH0611413A
公开(公告)日：1994-01-21
申请号：JP28111392
申请日：1992-09-28
Applicant: CANON KK
Inventor： SUGANO HIDEO , NAKAGAWA KATSUMI , KURODA YASUO , KIYOFUJI SHINICHI
IPC: G01M11/00 , G03G15/04 , G03G15/043 , H04N1/04 , H04N1/19
Abstract: PURPOSE:To provide a photoelectric converting device, which can simply sense the dispersion information without use of any all while document sheet, and offer a dispersion information sensing method for dispersion from bit to bit. CONSTITUTION:The image information on the surface of a document sheet is continuously photoelectric transduced by a photoelectric transducer element array 1 while the docunaent sheet irradiated with an illuminative light source 4 is moved by a feed roller 3. The roller 3 is installed facing the array 1, and a white or black reflex surface 5 is formed on the periphery of the roller 3 so as to photoelectric transduce the reflected light from the reflex surface 5 with the array 1, and dispersion of the conversion values is sensed as dispersion information from bit to bit.
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Patent Agency Ranking
公开(公告)号：JPH04139957A
公开(公告)日：1992-05-13
申请号：JP26041590
申请日：1990-10-01
Applicant: CANON KK
Inventor： KURODA YASUO
Abstract: PURPOSE:To improve the coding efficiency and to reduce the communication time by applying usual coding only to a required area in an original and converting other area into a data such as a white level data. CONSTITUTION:A clock pulse ADCLK is inputted sequentially to a counter circuit 3 in the transmission state. In this case, when the counter circuit 3 counts '120', since the contents of circuits 2,3 are coincident, a low level signal is outputted from a NAND gate IC 13 and a flip-flop IC 18 is reset. Thus, the output of the IC 18 goes again to a low level, the output of an AND gate IC 19 goes to a low level. That is, the part undesired to be sent in the original is converted forcibly into white level information. Thus, the communication time is reduced and the communication cost is suppressed.
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公开(公告)号：JPH0363696B2
公开(公告)日：1991-10-02
申请号：JP7492084
申请日：1984-04-16
Applicant: CANON KK
Inventor： SUGANO HIDEO , KURODA YASUO , NAKAGAWA KATSUMI , KYOFUJI SHINICHI
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公开(公告)号：JPS6348326B2
公开(公告)日：1988-09-28
申请号：JP11541580
申请日：1980-08-22
Applicant: CANON KK
Inventor： KURODA YASUO
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公开(公告)号：JPS61208369A
公开(公告)日：1986-09-16
申请号：JP4756885
申请日：1985-03-12
Applicant: CANON KK
Inventor： KURODA YASUO
Abstract: PURPOSE:To attain execution of image reading and quantization processing with excellent reliability by providing a means to maintain the maximum output value of a reading means, means to digitize the output of scanning a reference member, a means to store data as a correction signal, and a means to reproduce a reference value for the quantization. CONSTITUTION:A peak-detection circuit 11 is a circuit to detect and hold the peak value of an image signal inputted from an input terminal 10. And an A/D converter 12 digitizes the inputted image signal using a voltage VREF1 as its reference voltage. The data digitized by the converter 12 undergoes a bus controlling circuit 13 consisting of a microcomputer and others, and is stored in a memory 14. The data in the memory 14, when reading an image from the original, is converted by a D/A converter 16 and returns to be an analog data. For the conversion process, a voltage VREF2 which is a voltage divided by a resistor 15 from the output value of a peak-detection circuit 11, is used as a reference voltage. The output result of the D/A converter 16 is voltage-divided by the resistor 15, and is supplied to a comparator 17 as a reference value for the binarization of the image signal.
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