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公开(公告)号：AU5351694A
公开(公告)日：1994-04-26
申请号：AU5351694
申请日：1993-09-30
Applicant: COMPAQ COMPUTER CORP
Inventor： LANDRY JOHN A , MAYER DALE J , CULLEY PAUL R
Abstract: A multiplexed communication protocol for broadcasting interrupt, DMA and other miscellaneous data across a bus from a central peripheral device to a plurality of distributed peripheral devices associated with each processor in a multiprocessor computer system. The multiplexed bus includes a data portion and a status portion, where the status portion indicates one of several different cycle types executed on the bus, and where each cycle type further indicates the data asserted on the data portion. The cycle types further include address and data read and write cycles to allow access of the registers in the distributed devices via the multiplexed bus. Thus, system interrupt, address, data, DMA, NMI and miscellaneous cycles are defined where a system interrupt cycle is continually executed on consecutive cycles until interrupted by a request to execute another cycle type. The cycle sequence is implemented to insert system interrupt cycles between the address and data cycles to prevent significant channel latency when system interrupts occur.
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公开(公告)号：AU5169193A
公开(公告)日：1994-04-26
申请号：AU5169193
申请日：1993-09-29
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , LANDRY JOHN A
IPC: G06F13/24
Abstract: A computer system includes a filter at an interrupt request input for a microprocessor system. The interrupt signal filter suppresses any positive pulse that is shorter than 9 cycles of the host clock. Only signals that are asserted for at least 17 HCLK cycles are guaranteed passage to the interrupt controller to assert the interrupt request. In addition, any negative pulse on the IRQ signal is latched and extended for at least 9 cycles of the host clock. The filter thus suppresses noise to prevent unnecessary interrupts, and provides for enhanced detection of negative levels and rising edges for negative-going interrupt request signals.
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公开(公告)号：CA2005699A1
公开(公告)日：1990-08-21
申请号：CA2005699
申请日：1989-12-15
Applicant: COMPAQ COMPUTER CORP
Inventor： MAYER DALE J , ABDOO DAVID G
IPC: G06F12/06
Abstract: MEMORY BLOCK ADDRESS DETERMINATION CIRCUIT An adder and a comparator form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates the match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated board are provided and appropriate bus signals are developed.
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公开(公告)号：DE69832769T2
公开(公告)日：2006-07-13
申请号：DE69832769
申请日：1998-09-17
Applicant: COMPAQ COMPUTER CORP
Inventor： WITKOWSKI MICHAEL L , MAYER DALE J , WALKER WILLIAM J , ROLLER KIRK D , HARESKI PATRICIA E , KOTZUR GARY B
Abstract: A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more ofthe ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which ofthe plurality ofports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port. In an alternative embodiment bonded ports are assigned to packet source identifiers so as to achieve a relatively even distribution of source identifiers among the bonded ports. If bonded ports are assigned to particular source identifiers, then the traffic is preferably monitored and the assignments are periodically adjusted to achieve even distribution of packet flow on the bonded link. The bonded ports may have different bandwidths, in which case traffic is distributed on a proportionate basis.
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公开(公告)号：DE69731603T2
公开(公告)日：2005-04-21
申请号：DE69731603
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： WITKOWSKI MICHAEL L , CHANDLER GREGORY T , KHAN MOHAMMED A , KOTZUR GARY B , MAYER DALE J , WALKER WILLIAM J
Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port. During packet data transfer operations across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports. This processor is relieved of performing necessary overhead functions associated with the second bus and is thus freed to perform other important switch functions.
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Patent Agency Ranking
公开(公告)号：DE69731603D1
公开(公告)日：2004-12-23
申请号：DE69731603
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： WITKOWSKI MICHAEL L , CHANDLER GREGORY T , KHAN MOHAMMED A , KOTZUR GARY B , MAYER DALE J , WALKER WILLIAM J
Abstract: A network switch including a plurality of first network ports, a plurality of second network ports, a first bus, a second bus and a bridge interface coupled between the first and second buses. The first ports receive and transmit network data according to a first network protocol and the second ports receive and transmit network data according to a second network protocol. The first and second buses operate according to different bus standards. The bridge interface enables data transfer between the first and second buses and thus between the networks operating at different protocols. The switch includes a switch manager that controls the flow of network data and a processor for performing supervisory and control functions. The bridge interface includes receive buffers and transmit buffers assigned to respective ports. During packet data transfer operations across the first bus, the bridge interface emulates a first network port. During packet data transfer operations across the second bus, the bridge interface primarily acts as a slave to the second network ports by storing control lists for execution by the second network ports. This processor is relieved of performing necessary overhead functions associated with the second bus and is thus freed to perform other important switch functions.
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公开(公告)号：DE69731366D1
公开(公告)日：2004-12-02
申请号：DE69731366
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： HARESKI PATRICIA E , WALKER WILLIAM J , KOTZUR GARY B , MAYER DALE J , WITKOWSKI MICHAEL L
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公开(公告)号：DE69027348T2
公开(公告)日：1997-01-02
申请号：DE69027348
申请日：1990-01-19
Applicant: COMPAQ COMPUTER CORP
Inventor： ABDOO DAVID G , MAYER DALE J
IPC: G06F12/06
Abstract: An adder (204,206,208) and a comparator (242) form portions of a modular memory address block determination circuit. The starting address of the first block and the enable signal of the first block are added to produce the starting address of the second block. This procedure is repeated for each block. The determined starting address for each block is compared with the requested memory address and, unless the block is inhibited or disabled, if equal a signal indicates a match. The circuit is used on a circuit board which emulates three conventionally separate memory circuit boards. The registers for each emulated circuit board are provided and appropriate bus signals are developed.
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公开(公告)号：DE69832769D1
公开(公告)日：2006-01-19
申请号：DE69832769
申请日：1998-09-17
Applicant: COMPAQ COMPUTER CORP
Inventor： WITKOWSKI MICHAEL L , MAYER DALE J , WALKER WILLIAM J , ROLLER KIRK D , HARESKI PATRICIA E , KOTZUR GARY B
Abstract: A network communication device including port control circuitry for controlling packet flow between the ports of the device, where the port control circuitry includes a port manager that directs packets between the ports and port bonding circuitry that bonds two or more ofthe ports into a bonded port set. For each packet to be sent via the bonded port set, the port bonding circuitry selects one of the bonded ports for transmitting the packet. More than one bonded port set may be defined in a given communication device, and each bonded port set may include from two ports up to all the ports of the device, as long as each port is included in only one bonded port set. One or more port bonding registers are provided to identify which ofthe plurality ofports are bonded in each bonded port set. In one embodiment, the bonded ports are selected on a packet by packet basis so as to achieve a relatively even distribution of packets sent by each bonded port. In an alternative embodiment bonded ports are assigned to packet source identifiers so as to achieve a relatively even distribution of source identifiers among the bonded ports. If bonded ports are assigned to particular source identifiers, then the traffic is preferably monitored and the assignments are periodically adjusted to achieve even distribution of packet flow on the bonded link. The bonded ports may have different bandwidths, in which case traffic is distributed on a proportionate basis.
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公开(公告)号：DE69731519T2
公开(公告)日：2005-12-01
申请号：DE69731519
申请日：1997-12-30
Applicant: COMPAQ COMPUTER CORP
Inventor： WALKER WILLIAM J , KOTZUR GARY B , WITKOWSKI MICHAEL L , HARESKI PATRICIA E , MAYER DALE J
Abstract: A multiport polling system for a network switch including a plurality of network ports, each including receive and transmit buffers. Each port includes port status logic for providing status signals indicative of whether a corresponding port has received data from a network device and whether a corresponding port has available space to receive data to transmit to a network device. The network switch further includes a switch manager for controlling data flow between the ports. The switch manager includes polling logic for periodically polling the port status logic of each port for receiving the status signals, and a memory for storing values indicative of the status signals for each port. In this manner, all of the ports are simultaneously polled in a singe query and the receive and transmit status of each port is maintained in the memory. This facilitates arbitration and control logic, which continuously reviews the memory to determine when to retrieve data from a source port and when to transmit data to one or more destination ports. The ports are preferably implemented with quad cascade devices for providing multiplexed status signals.
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