公开(公告)号：CA2026770A1

公开(公告)日：1991-05-04

申请号：CA2026770

申请日：1990-10-02

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  CULLEY PAUL R

IPC: G06F13/26 ,  G06F9/46

Abstract: Two independently operating microprocessors share common control, data and address buses. A first of the microprocessors is assigned, when it is on the buses, to respond to all maskable interrupts by causing placement of an interrupt vector on the bus at the start of the next bus cycle. When the second microprocessor is on the buses and a maskable interrupt is received, the start of the next bus cycle is inhibited from causing an interrupt vector to be placed on the bus.

公开(公告)号：CA2119174C

公开(公告)日：1998-10-20

申请号：CA2119174

申请日：1994-03-16

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  THOME GARY W ,  SANTELER PAUL A ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16 ,  G06F12/02

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

公开(公告)号：AU5297993A

公开(公告)日：1994-04-26

申请号：AU5297993

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  WOLFORD JEFF W ,  FRY WALTER G ,  TIPLEY ROGER E

IPC: G06F11/16 ,  G06F11/20

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

公开(公告)号：JPH10154064A

公开(公告)日：1998-06-09

申请号：JP31222197

申请日：1997-11-13

Applicant: COMPAQ COMPUTER CORP

Inventor： TRAN THANH T ,  LANDRY JOHN A ,  WATTS ROBERT F

IPC: G06F3/16 ,  G10H1/00 ,  H04S7/00

Abstract: PROBLEM TO BE SOLVED: To simultaneously perform a full duplex speakerphone operation and audio reproduction like a game, etc., without an external Codec. SOLUTION: At the time of a speakerphone mode, a multiplexer 75 selects a speakerphone audio line 77, a signal sent from a DSP(digital signal processor) interface is supplied to the left channel of a D/A converter 63 and outputted as a left audio output via a mixer 59. When synthetic audio is desired to be reproduced even in a speakerphone mode, a multiplexer 81 selects the output of a mixer 79 a monotone digital signal which represents the sum of left and right audio channels which are synthesized is outputted as a right audio output via the right channel of the converter 63 and the mixer 59. Therefore, audio reproduction of a game, etc., is heard through the right speaker, while audio reproduction of a full duplex speakerphone operation is heard through the left speaker.

公开(公告)号：AT151184T

公开(公告)日：1997-04-15

申请号：AT93924908

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A

IPC: G06F11/00 ,  G06F11/22 ,  G06F15/177 ,  G06F15/16

Abstract: A multiprocessor computer system includes fault tolerant power up logic for finding a functioning CPU to operate as logical CPU0. Each microprocessor has a physical location designation which remains constant. When the system is powered up, all of the CPUs except the CPU in physical slot 0 (CPU P0) are initially placed in an inactive sleep state. The microprocessor in physical location 0 performs its power on self test (POST), and if the CPU functions properly, the CPU is designated as logical CPU0 (CPU L0). The microprocessor then awakens the remaining CPUs and boots up the rest of the computer system. If CPU P0 is not functioning properly, after a given time period the system awakens the processor in the next physical location and repeats the process of testing the CPU. The process repeats until an operating microprocessor is found to perform the CPU L0 functions.

公开(公告)号：AU5351594A

公开(公告)日：1994-04-26

申请号：AU5351594

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORP

Inventor： MAYER DALE J ,  LANDRY JOHN A ,  CULLEY PAUL R

IPC: G06F13/24

公开(公告)号：CA2026771A1

公开(公告)日：1991-05-04

申请号：CA2026771

申请日：1990-10-02

Applicant: COMPAQ COMPUTER CORP

Inventor： IZQUIERDO JAVIER F ,  LANDRY JOHN A

IPC: G06F12/02 ,  G06F12/08 ,  G06F15/17 ,  G06F13/14 ,  G06F9/46

Abstract: A method for communication between multiple processors using registers that are accessed by four register select lines which are translated from the original system address. The address translation is performed off of the main processor board to reduce loading effects on the local bus and reduces the pin count of processor board. A signal representing which of the processors is currently active is used as a pseudo address line for the purpose of the translation. The original addresses of the I/O registers may be either input/output or memory mapped.

公开(公告)号：DE69427421D1

公开(公告)日：2001-07-19

申请号：DE69427421

申请日：1994-03-22

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  SANTELER PAUL A ,  THOME GARY W ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

公开(公告)号：AT202227T

公开(公告)日：2001-06-15

申请号：AT94302014

申请日：1994-03-22

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  SANTELER PAUL A ,  THOME GARY W ,  BONELLA RANDY M ,  COLLINS MICHAEL J

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

Abstract: A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller can utilize different speed memory devices and run each memory device at its desired optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine reaches has completed its function, it notifies a related state machine that it can now proceed and proceeds to wait for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory controller utilizes differing speed memory devices, such as 60 ns and 80 ns, on an individual basis, with each memory device operating at its full designed rate. The speed of the memory is stored for each 128 kbyte block of memory and used when the memory cycle is occurring to redirect a state machine, accomplishing a timing change of the memory devices.

公开(公告)号：AU5351694A

公开(公告)日：1994-04-26

申请号：AU5351694

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORP

Inventor： LANDRY JOHN A ,  MAYER DALE J ,  CULLEY PAUL R

IPC: G06F13/32 ,  G06F13/42

Abstract: A multiplexed communication protocol for broadcasting interrupt, DMA and other miscellaneous data across a bus from a central peripheral device to a plurality of distributed peripheral devices associated with each processor in a multiprocessor computer system. The multiplexed bus includes a data portion and a status portion, where the status portion indicates one of several different cycle types executed on the bus, and where each cycle type further indicates the data asserted on the data portion. The cycle types further include address and data read and write cycles to allow access of the registers in the distributed devices via the multiplexed bus. Thus, system interrupt, address, data, DMA, NMI and miscellaneous cycles are defined where a system interrupt cycle is continually executed on consecutive cycles until interrupted by a request to execute another cycle type. The cycle sequence is implemented to insert system interrupt cycles between the address and data cycles to prevent significant channel latency when system interrupts occur.