公开(公告)号：WO0072575A3

公开(公告)日：2001-03-01

申请号：PCT/US0014222

申请日：2000-05-24

Applicant: HEWLETT PACKARD CO ,  IBM ,  COMPAQ COMPUTER CORP ,  ADAPTEC INC ,  GARCIA DAVID J ,  CULLEY PAUL R ,  RECIO RENATO JOHN ,  BENNER ALAN F ,  KRAUSE MICHAEL

Inventor： GARCIA DAVID J ,  CULLEY PAUL R ,  RECIO RENATO JOHN ,  BENNER ALAN F ,  KRAUSE MICHAEL

IPC: H04L12/56 ,  G06F9/40 ,  G06F9/46 ,  G06F13/00 ,  G06F15/16 ,  G06F15/163 ,  G06F15/167 ,  G06F15/173 ,  H02H3/05 ,  H04J3/24 ,  H04L5/14 ,  H04N20060101

CPC classification number: G06F9/544 ,  H04L45/46

Abstract: A distributed computer sytem (500) includes a source endnode (502) including a source process (508) which produces message data and a send work queue (516a) having work queue elements that describe the message data for sending. A destination endnode (504) includes a destination process (510, 512) and a receive work queue (518b, 520b) having work queue elements that describe where to place incoming message data. A communication fabric (524) provides communication between the source endnode and the destination endnode. An end-to-end context (530, 534) is provided at the source endnode and the destination endnode storing state information to ensure the reception and sequencing of message data sent from the source endnode to the destination endnode permitting reliable datagram service between the source endnode and the destination endnode.

Abstract translation: 分布式计算机系统（500）包括源端节点（502），源节点（502）包括产生消息数据的源过程（508）和具有描述用于发送的消息数据的工作队列元素的发送工作队列（516a）。 目的地节点（504）包括具有描述入站消息数据的位置的工作队列元素的目的地处理（510,512）和接收工作队列（518b，520b）。 通信结构（524）提供源端节点和目的端节点之间的通信。 源终端上下文（530,534）被提供在源端节点和目的地端节点存储状态信息，以确保从源端节点发送到目的端节点的消息数据的接收和排序，从而允许源之间的可靠数据报服务 endnode和目标endnode。

公开(公告)号：JPH10124449A

公开(公告)日：1998-05-15

申请号：JP16201797

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： GOODRUM ALAN L ,  MACLAREN JOHN M ,  CULLEY PAUL R

IPC: G06F13/36 ,  G06F12/08 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To improve whole computer system efficiency by providing a bridge device which transmits a data request from a first device to a second device, and returns the requested data to the first device. SOLUTION: This system is provided with a first device on a first data bus, second device on a second data bus, and bridge device which transmits a request from the first device to the second device, and returns the requested data to the first device. The bridge device includes a first data storage buffer which stores data requested by the first device during the first request and a second data storage buffer which simultaneously stores the data requested by the first device during the second request. A computer system 10 includes a primary PCI bus 24, and this is connected with bridge chips 26a and 26b in common design 26.

公开(公告)号：JPH10116208A

公开(公告)日：1998-05-06

申请号：JP16207097

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： GOODRUM ALAN L ,  AUTOR JEFFREY S ,  CULLEY PAUL R ,  MILLER JOSEPH P ,  TAVALLAEI SIAMAK ,  BASILE BARRY S ,  RICHARD ELIZABETH A ,  ROSE ERIC E

IPC: G06F11/30 ,  G06F11/00 ,  G06F11/10 ,  G06F11/20 ,  G06F11/22 ,  G06F11/267 ,  G06F11/34

Abstract: PROBLEM TO BE SOLVED: To isolate a device where a fault has occurred by discriminating the device in the faulty state by a fault isolation controller in response to a fault state. SOLUTION: A system controller/host bridge circuit 18 controls access to a system memory 20, which is coupled with a local bus 22 together with a CPU 14 and a level-2/cache (L2 cache) 16. Information that a nonvolatile random access memory(NVRAM) 70 holds, does not volatilize even when the computer system is powered OFF. Then, an automatic server recovery(ASR) timer 72 monitors inactive operation of the computer system. When the system is locked up, the ASR timer 72 turns off about 10 minutes later. Then a keyboard controller 21 monitors a keyboard 19 to detect a depressed key.

公开(公告)号：JPH1055336A

公开(公告)日：1998-02-24

申请号：JP16210097

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： GOODRUM ALAN L ,  MACLAREN JOHN M ,  PETTEY CHRISTOPHER J ,  CULLEY PAUL R

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To improve an overall efficiency of a computer system by starting a supply of data after a requester device acquires again a control right of a 2nd data bus while a data memory device is supplying the requested data to a bridge device. SOLUTION: A delay completion queue(DCQ) 144 stores the delay completion information which is supplied from an upstream chip in response to the delay request transaction that is generated on a secondary bus 32. The DCQ 144 has eight completion buffers, for example, and can hold the completion information on eight line caches at most against a single delay request. In regard to a delay read transaction, the retrieval of the data requested by a requester device is started before a target device stops the supply of data to the DCQ 144 and a data stream is established between a primary bus and the bus 32.

公开(公告)号：JPH10124188A

公开(公告)日：1998-05-15

申请号：JP16211597

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： CULLEY PAUL R ,  GOODRUM ALAN L ,  CHOW RAYMOND Y L ,  BASILE BARRY S

IPC: G06F1/26 ,  G06F1/18 ,  G06F12/08 ,  G06F13/36 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To enable inserting and ejecting an extention card to/from an extention slot while a computer system is kept in the power-up state by adjusting power supply to a connector based on a clamp connecting state. SOLUTION: Two extention boxes 30a and 30b are provided with six hot-plug- type slots 36 (36a-36f) where a conventional extention card is attached and detached while the computer system is being power-upped by them. A corresponding lever has to be opened in order to detach/insert the extention card from/to one of the slots 36. That is, a latch has to be removed but the power of the corresponding slot 36 is kept down while the lever is opened. When the lever fixed to the slot 36 is opened, the computer system senses it so as to power down the system before the card can be detached from the slot 36.

公开(公告)号：JPH1083231A

公开(公告)日：1998-03-31

申请号：JP16202497

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： GOODRUM ALAN L ,  CULLEY PAUL R ,  CHOW RAYMOND Y L ,  BASILE BARRY S ,  WALDORF RICHARD O ,  COOK PAMELA M ,  MAR CLARENCE Y

IPC: G06F1/26 ,  G06F1/18 ,  G06F1/24 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To stabilize the operation of the card by backing up the card, supplying a clock signal to the card, and then electrically coupling a communication link with the card when the card is inserted into a card slot of a computer system. SOLUTION: Each extension box 30 has six hot plug slots 36, which electrically connects extension cards. To one slot 34 of the extension box, a card which has a bridge chip is connected. Each hot plug slot 36 has a switch circuit 41, and consequently the slot 36 and a PCI bus are connected and disconnected. Then electric power and clock signals are supplied to the circuit card and after the electric power and clock signals are both supplied to the circuit card, the communication link is electrically coupled with the circuit card. Here, delay is so given preferably that the electric power of the circuit card becomes stable before the electric coupling and further the circuit on the circuit card synchronizes with the clock signal before the electric coupling.

公开(公告)号：JPH1055334A

公开(公告)日：1998-02-24

申请号：JP16206397

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： RAMSEY JENS K ,  GOODRUM ALAN L ,  CULLEY PAUL R

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/364

Abstract: PROBLEM TO BE SOLVED: To prevent a CPU from spending its time for waiting for the end of an I/O access and also to prevent other bus masters from being kept waiting for a long time by performing an arbitration among the bus devices via an arbiter and also performing the arbitration between the CPU and another bus device when the CPU has a request. SOLUTION: The PCI arbiters 116 and 124 are added to the bridge chips 26 and 48. All masters placed on a PCI bus 32 have the same priority as the chip 48 in an arbitration scheme of 2nd level that is carried out by the arbiter 124 in its normal operation. Then an arbitration protocol of 2nd level includes a delayed request given from a CPU, a request given from a master having a retry and an arbitration scheme of 1st level, i.e., a round-rofin scheme among the masters which are selected by the arbitration scheme of 2nd level.

公开(公告)号：JPH10143387A

公开(公告)日：1998-05-29

申请号：JP29744697

申请日：1997-10-29

Applicant: COMPAQ COMPUTER CORP

Inventor： CULLEY PAUL R ,  MILLER JOSEPH P ,  HULL DANIEL S ,  TAVALLAEI SIAMAK

IPC: G06F11/22 ,  G06F11/07

Abstract: PROBLEM TO BE SOLVED: To make a computer system possible to diagnose the fault of plural circuits, bus, etc., in the computer system. SOLUTION: A system management SMR 10 of the computer system monitors each circuit and bus, generates fault information when a fault occurs and stores the corresponding fault information in a memory 32 by relating the fault information with the circuit and the bus where the fault has occurred. The fault information includes an improper state of an internal clock of the circuit, a high temperature state, an overvoltage state and the bus error state when no refresh state is generated within a prescribed time.

公开(公告)号：JPH1063615A

公开(公告)日：1998-03-06

申请号：JP16211097

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： GOODRUM ALAN L ,  CULLEY PAUL R

IPC: G06F13/36 ,  G06F11/34 ,  G06F13/362

Abstract: PROBLEM TO BE SOLVED: To determine different bus performance parameters by counting a full period determined in advance and measuring the using state of a bus for data transfer during that full period. SOLUTION: A bridge chip is designed so as to be used while being paired, and a PCI-PCI bridge is formed between a 1st-order PCT bus 24 and a 2nd-order PCI bus 32. Namely, a bridge chip 26 connects the 1st-order PCI bus 24 to a cable 28. Besides, a 2nd-order PCI-PCI bridge 48 is provided inside an extended box and connects the cable 28 to the 2nd-order PCI bus 32. Then, the full period determined in advance is counted by a bus monitor 106 of the bridge chip 26 and a bus monitor 127 of the 2nd PCI-PCI bridge 48, and the using states of the respective buses 24 and 32 for data transfer during that full period are measured. Thus, the different bus performance parameters can be determined.

公开(公告)号：JPH1055338A

公开(公告)日：1998-02-24

申请号：JP16207697

申请日：1997-06-05

Applicant: COMPAQ COMPUTER CORP

Inventor： GOODRUM ALAN L ,  RAMSEY JENS K ,  CULLEY PAUL R ,  MILLER JOSEPH P

IPC: G06F13/36 ,  G06F1/12 ,  G06F13/40 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To properly transmit data among two devices by generating a 1st and a 2nd clocks by a 1st and a 2nd devices to give these clocks to other devices and preparing a receiving interface to the 1st device to synchronize the received data with the 1st clock. SOLUTION: Bridge chips 26 and 48 are used in a pair, and a PCI-PCI bridge is formed between a primary PCI bus 24 and a secondary PCI bus 32. A clock generator contained in the chip 26 generates the clocks based on a clock PCICLK 1 put on the bus 24, and one of these generated clocks is supplied to the clock generator of the chip 48 of the downstream side via a cable 28. The clock generator of the chip 48 generates a PCI clock in an extended box 30 with the same frequency as the bus 24. Thus, both bridges 26 and 48 operate by the same frequency.