公开(公告)号：WO1994026520A1

公开(公告)日：1994-11-24

申请号：PCT/US1994005059

申请日：1994-05-03

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  STORTZ, James, L.

IPC: B41J02/045

CPC classification number: B41J2/04543 ,  B41J2/04581 ,  B41J2202/10

Abstract: A differential drive system is used to actuate an ink jet printhead (10) having a spaced, parallel series of internal ink receiving channels opening outwardly through ink discharge orifices formed in the printhead body (12). The channels (32) are laterally bounded by a spaced series of piezoelectrically deflectable internal sidewall actuator sections of the printhead body (12) interdigitated with the channels. The printhead body (12) is specially configured to facilitate wiring access to spaced apart first and second electrical connection portions on each of the actuators. Electrical leads (56) from a first controller (58) are connected to the first actuator portions and are ganged in groups that are selectively connected to a driving voltage source, or to ground, by the first controller (58). A second controller (70) has a first set of electrical leads (68) similarly ganged in groups and connected to a first set of the second actuator portions, and a second set of unganged electrical leads individually connected to the rest of the second actuator portions. The second controller is operative to selectively connect any of its individual leads, or any of its ganged lead groups, to the driving voltage source or to ground. In conjunction with the dual controllers (58, 70), this combination of ganged and individually addressable leads connected to the first and second actuator portions permits the actuators to be differentially driven in a manner digitally synthesizing a more complex bipolar drive system.

Abstract translation: 差分驱动系统用于致动喷墨打印头（10），其具有间隔开的，平行的内部油墨接收通道系列，其通过形成在打印头主体（12）中的排墨孔向外打开。 通道（32）由与通道交叉指向的打印头主体（12）的间隔开的一系列压电可偏转的内部侧壁致动器部分横向界定。 打印头本体（12）被特别地配置成便于接近每个致动器上间隔开的第一和第二电连接部分。 来自第一控制器（58）的电引线（56）连接到第一致动器部分，并且被组合成由第一控制器（58）选择性地连接到驱动电压源或接地的组。 第二控制器（70）具有类似地组合并连接到第一组第二致动器部分的第一组电引线（68）和与第二致动器部分的其余部分分别连接的第二组非接地电引线 。 第二控制器可操作以选择地将其各个引线或其任何组合的引线组连接到驱动电压源或接地。 结合双控制器（58,70），连接到第一和第二致动器部分的组合和可单独寻址的引线的组合允许致动器以数字合成更复杂的双极驱动系统的方式进行差分驱动。

公开(公告)号：WO1994008305A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009367

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  ALEXANDER, Dennis, J. ,  GALLOWAY, William, C.

IPC: G06F13/40

CPC classification number: H04L12/403 ,  G06F13/4072 ,  H04L12/40

Abstract: A method of disabling active termination on an SCSI device when the SCSI device is not at the terminal end of the SCSI bus chain, and circuitry for accomplishing that method. An SCSI device has selectable active termination. When the SCSI device is off, the active termination circuitry is powered by the termination power line of the SCSI bus, and so the termination circuitry does not require power to the SCSI device to work properly. The SCSI device has two ports for connection in the SCSI chain, and the SCSI device detects whether a device is present on each of those ports by detecting whether a line that pulled to ground has in fact been pulled to ground. If both ports are connected to SCSI device, then the SCSI device disables its active termination using the disconnect input of the circuit it uses for active termination of the SCSI bus. Further, the SCSI device can communicate whether devices are connected to each of its SCSI ports to a host computer system via the system bus.

Abstract translation: 当SCSI设备不在SCSI总线链的终端时，禁用SCSI设备上的主动终止的方法以及用于实现该方法的电路。 SCSI设备可选择主动终止。 当SCSI设备关闭时，主动终端电路由SCSI总线的终端电源线供电，因此终端电路不需要SCSI设备的电源正常工作。 SCSI设备具有用于SCSI链中连接的两个端口，并且SCSI设备通过检测是否将拉到地的线实际上被拉到地来检测每个端口上是否存在设备。 如果两个端口都连接到SCSI设备，则SCSI设备将使用其用于主动终止SCSI总线的电路的断开输入来禁用其主动终端。 此外，SCSI设备可以通过系统总线来传送设备是否连接到其每个SCSI端口到主机计算机系统。

公开(公告)号：WO1994008304A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009369

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TAYLOR, Mark ,  CULLEY, Paul, R. ,  MELO, Maria, L. ,  TIPLEY, Roger, E.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008297A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009432

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WOLFORD, Jeff, W. ,  FRY, Walter, G.

IPC: G06F12/08

CPC classification number: G06F12/0831

Abstract: A method and apparatus for performing concurrent operations on the host bus, expansion bus, and local I/O bus as well as the processor bus connecting the processor and cache system to increase computer system efficiency. A plurality of CPU boards are coupled to a host bus which in turn is coupled to an expansion bus through a bus controller. Each CPU board includes a processor connected to a cache system including a cache controller and cache memory. The cache system interfaces to the host bus through address and data buffers controlled by cache interface logic. Distributed system peripheral (DSP) logic comprising various ports, timers, and interrupt controller logic is coupled to the cache system, data buffers, and cache interface logic by a local I/O bus. The computer system supports various areas of concurrent operation, including concurrent local I/O cycles, host bus snoop cycles and CPU requests, as well as concurrent expansion bus reads with snooped host bus cycles.

Abstract translation: 一种在主机总线，扩展总线和本地I / O总线上执行并行操作的方法和装置，以及连接处理器和缓存系统的处理器总线，以提高计算机系统的效率。 多个CPU板耦合到主机总线，主机总线又通过总线控制器耦合到扩展总线。 每个CPU板包括连接到包括高速缓存控制器和高速缓冲存储器的高速缓存系统的处理器。 缓存系统通过由缓存接口逻辑控制的地址和数据缓冲器与主机总线进行接口。 包括各种端口，定时器和中断控制器逻辑的分布式系统外设（DSP）逻辑通过本地I / O总线耦合到高速缓存系统，数据缓冲器和高速缓存接口逻辑。 计算机系统支持并行操作的各个领域，包括并发本地I / O周期，主机总线侦听周期和CPU请求以及带有主机总线周期的并发扩展总线读取。

公开(公告)号：WO1994008288A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009072

申请日：1993-09-22

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CROSSWY, William, C. ,  BARRON, Dwight, L. ,  ABMAYR, David, L. ,  ROSENBLUM, Harvey, M. ,  BURCKHARTT, David, M.

IPC: G06F09/445

CPC classification number: G06F9/4406 ,  G06F9/4411 ,  G06F9/44521

Abstract: A computer system which includes certain minimum capabilities in a system ROM. Device driver software is located in the system ROM or adapter ROM's. On boot the computer system collects these device drivers from ROM to develop a minimal system. If a removable medium such as a floppy disk or CD-ROM is present a configuration mode in entered when final driver files and operating system modules are stored on a selected hard disk. After this storage the device driver modules and operating system modules necessary to develop a boot image of the operating system are gathered and linked. The boot image is generated and stored, allowing use on the following boot operations. The computer system detects device changes and rebuilds the boot image as necessary. If the devices have remained the same the previously stored boot image is loaded and operating system execution commences.

Abstract translation: 包括系统ROM中的某些最小能力的计算机系统。 设备驱动程序软件位于系统ROM或适配器ROM中。 在引导时，计算机系统从ROM收集这些设备驱动程序以开发最小的系统。 如果在最终的驱动程序文件和操作系统模块存储在所选择的硬盘上时，如可移动介质（如软盘或CD-ROM）存在输入的配置模式。 存储后，收集并链接开发操作系统引导映像所需的设备驱动程序模块和操作系统模块。 引导映像生成并存储，允许在以下引导操作中使用。 计算机系统检测设备更改并根据需要重新构建引导映像。 如果设备保持不变，则先前存储的引导映像将被加载并且操作系统执行开始。

公开(公告)号：WO1993022730A1

公开(公告)日：1993-11-11

申请号：PCT/US1993004005

申请日：1993-04-28

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  STANCIL, Charles, J.

IPC: G06F13/40

CPC classification number: G06F13/4063 ,  G06F15/7832

Abstract: A computer system can be upgraded from a 386 main CPU to a 486 microprocessor without exchanging the processor card or removing the 386 microprocessor. The computer includes a single empty socket which can be fitted with a 486SX, 487SX, or 486DX microprocessor. Any of these microprocessors can be plugged into the socket, which causes the cache system which includes an 82395 to enter a tri-state test mode and suspends the operation of the main CPU. To correct for the variations in the pin arrangements of each processor, various system signals are routed using switches to different pins for different microprocessors. In addition, specific system signals are rerouted among the system components using a set of six switches to provide for proper operation when the socket is empty and when it is occupied. By appropriately setting all of the switches, the correct signals are provided to each pin of the upgrade microprocessor. While the cache system remains in test mode, the main CPU remains fundamentally inactive, and the upgrade processor controls the computer system.

Abstract translation: 计算机系统可以从386主CPU升级到486微处理器，而无需更换处理器卡或卸下386微处理器。 计算机包括一个可以安装486SX，487SX或486DX微处理器的空插槽。 任何这些微处理器都可以插入插座，这使得包括82395的缓存系统进入三态测试模式并暂停主CPU的操作。 为了校正每个处理器的引脚布置的变化，各种系统信号使用开关被路由到用于不同微处理器的不同引脚。 此外，使用一组六个开关在系统组件之间重新路由特定的系统信号，以在插座为空和占用时提供正确的操作。 通过适当地设置所有开关，将正确的信号提供给升级微处理器的每个引脚。 当缓存系统保持测试模式时，主CPU仍然基本不活动，升级处理器控制计算机系统。

公开(公告)号：WO1993022141A1

公开(公告)日：1993-11-11

申请号：PCT/US1993004247

申请日：1993-05-05

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  HAYES, Donald, J. ,  COX, W., Royall

IPC: B41J02/16

CPC classification number: B41J2/1634 ,  B23K26/384 ,  B41J2/162 ,  B41J2/1623 ,  Y10T29/49401

Abstract: Method of forming an orifice array for an ink jet printhead (29). Excimer laser radiation is used to ablate an orifice array in a cover plate (10) having a removable backing (16), a front side layer (12) formed from either an ablatable inactive material such as polyimide, a non-wettable material doped to absorb excimer radiation, or an ablatable inactive material such as polyimide with a very thin surface layer of a non-wettable material, and an intermediate layer (14) formed from an adhesive material. First, a series of generally square indentations (26) approximately 80 mu m on each side and which extends through the removable backing (16) and the intermediate layer (14) and partially through the front side layer (12) exposing an interior surface (27) of the front side is formed at spaced locations along the back side surface of the cover plate (10). Next, a corresponding series of generally circular apertures (28) approximately 40 mu m in diameter, each positioned in the general center of the corresponding indentation (26) and extending through the front side layer (12) is formed in the cover plate (10).

Abstract translation: 形成用于喷墨打印头（29）的孔阵列的方法。 准分子激光辐射用于消除具有可移除背衬（16）的盖板（10）中的孔阵列，由可消融的非活性材料（例如聚酰亚胺）形成的前侧层（12），掺杂至 吸收准分子辐射或具有非常薄的非可湿性材料表面层的可消融的非活性材料如聚酰亚胺以及由粘合剂材料形成的中间层（14）。 首先，在每一侧上大约为80μm的一系列大致平方的凹口（26），其延伸穿过可移去的背衬（16）和中间层（14）并部分地穿过前侧层（12），暴露出内表面 前侧的边缘27）沿着盖板（10）的背侧表面的间隔位置处形成。 接下来，在盖板（10）中形成相应的一系列大致圆形的孔（28），其直径大约为40μm，每个位于对应的凹口（26）的大致中心并延伸穿过前侧层（12） ）。

公开(公告)号：WO1992014194A1

公开(公告)日：1992-08-20

申请号：PCT/US1992000710

申请日：1992-01-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  BHAGAT, Gopal, C.

IPC: G03G15/16

CPC classification number: G03G15/1675

Abstract: An electrically biased attracter roller (60) is utilized in an electrophotographic image reproduction machine (10a), in place of a conventional corotron device, to electrically transfer toner from the side of a rotating photoconductor drum (14a) onto a side surface of paper stock (36a) being operatively fed through the machine. The charged roller (60) is spring-biased into forcible side-to-side engagement with the drum (14a) and is frictionally rotated by the drum. The paper stock (36a) is fed between the rotating roller (60) and drum (14a) and, by a combination of pressure and electrical attractive force, the roller (60) very efficiently transfers toner from the drum (14a) to the paper. To further improve the overall effectiveness of the attracter roller (60), a humidity compensation system (86) is provided and is operative to automatically adjust the bias voltage of the roller (60) and thus the electrical toner attraction force thereof, in response to sensed humidity variations within the machine housing.

公开(公告)号：WO1992013786A2

公开(公告)日：1992-08-20

申请号：PCT/US1992000715

申请日：1992-01-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  SELLERS, Charles, A.

IPC: B65H03/44

CPC classification number: B65H1/266 ,  B65H1/28 ,  G03G15/6502

Abstract: A dual bin envelope tray (30) is adapted to support, in a side-by-side relationship, two stacks (32, 34) of envelopes which may be of different sizes. The envelope tray is configured to be interchangeable with the conventional paper supply tray of a printing device, such as a printer, copier or the like, and may be inserted directly into the printing device housing opening from which the paper tray is removed. Cooperating driving and driven structures, respectively disposed within the housing and on the envelope tray, function to sequentially feed the envelopes in either stack thereof into the printing device housing for passage through its existing printing and paper exit paths.

Abstract translation: 用于信封的双隔间托盘（30）被设计为并排支撑两个尺寸不同的信封（32,34）。 信封托盘被构造成可与诸如打印机，复印机等的打印装置的常规纸张装载托盘互换，并且可被直接馈送到打印机壳体中。 因此卸下纸张装入托盘。 分别放置在壳体内和信封托盘上的配合驱动结构和从动结构操作以将两个堆叠中的一个的信封装载到打印装置的壳体中，使得 他们通过现有的打印和退出路径。

公开(公告)号：WO1996028916A1

公开(公告)日：1996-09-19

申请号：PCT/US1996003368

申请日：1996-03-12

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  SCOTT, Craig, M. ,  WANG, Li, Tung ,  BENNETT, Arthur, T. ,  NOURI, Ahmad

IPC: H04L12/44

CPC classification number: H04L12/46 ,  H04L12/44 ,  H04L49/25 ,  H04L49/351

Abstract: A network (10) includes several local networks (32, 34, 36). Each local network (32, 34, 36) includes a repeater (12, 16, 20) coupled to data devices (14, 18, 22). The combination of the repeater (12, 16, 20) and the data devices (14, 18, 22) form a collision domain for managing communications within the local network (32, 34, 36). Uplink modules (40, 44) manage communications between the local networks (32, 34, 36) by isolating collision domains and generating collision indications when messages cannot be transmitted. The uplink modules (40, 44) may also implement bridging, routing, or filtering capabilities that inhibit transmission of an intra-network message beyond its local network (32, 34, 36).

Abstract translation: 网络（10）包括多个本地网络（32,34,36）。 每个本地网络（32,34,36）包括耦合到数据设备（14,18,22）的中继器（12,16,20）。 中继器（12,16,20）和数据设备（14,18,22）的组合形成用于管理本地网络（32,34,36）内的通信的冲突域。 上行链路模块（40,44）通过隔离冲突域来管理本地网络（32,34,36）之间的通信，并且当消息不能被发送时产生冲突指示。 上行链路模块（40,44）还可以实现阻止网络内消息超出其本地网络（32,34,36）的传输的桥接，路由或过滤能力。