公开(公告)号：WO1994008304A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009369

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TAYLOR, Mark ,  CULLEY, Paul, R. ,  MELO, Maria, L. ,  TIPLEY, Roger, E.

IPC: G06F13/364

CPC classification number: G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008301A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009186

申请日：1993-09-24

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

Abstract translation: 用于确定多个CPU中的哪一个接收优先权以成为多处理器系统中的主机总线的总线的三个优先级方案，以及用于将控制从一个总线主机传送到另一个总线主机的仲裁方案。 每个优先排序方案优先考虑n个元素，其中总共（n / 2）x（n-1）个优先级位监视每对元素之间的相对优先级。 当与该元素相关联的n-1个优先级位中的每一个指向它时，元素接收最高优先级。 在仲裁方案中，主机总线的当前总线主机确定主机总线的控制何时发生，由优先级排列方案之一决定。 仲裁方案给予EISA总线主机，RAM刷新和DMA优先于作为总线主机的CPU，并允许临时总线主机中断当前总线主机以执行回写高速缓存干预周期。 仲裁方案还支持在尝试锁定循环时中止CPU的地址流水线，突发，拆分事务和预留。 地址流水线允许下一个总线主机在下一个总线主机的数据传输阶段开始之前断言其地址和状态信号。 拆分事务允许CPU向EISA总线发布读取，以将主机总线仲裁到另一个设备，而不需要重新仲裁主机总线来检索数据。 即使主机总线被其他设备控制，数据在空闲时也在主机总线上被断言。

公开(公告)号：WO1994008296A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009366

申请日：1993-09-29

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  CULLEY, Paul, R. ,  TAYLOR, Mark

IPC: G06F12/02

CPC classification number: G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

Abstract: Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.

Abstract translation: 双缓存操作，以减少扩展总线主机访问计算机系统的主机总线上的主存储器时的主机总线保持时间。 耦合在主存储器和扩展总线之间的系统数据缓冲器包括256位双重读写缓冲器。 耦合到双读和写缓冲器和扩展总线的存储器控​​制器包括对应于双缓冲器的主地址和副地址锁存器。 存储器控制器检测对主存储器的访问，将扩展总线地址与主地址和辅助地址进行比较，并相应地控制双读和写缓冲器以及主地址和副地址锁存器。 在写入操作期间，要写入同一行存储器的数据被写入双写缓冲器中的第一个，直到在将数据传送到主存储器之前写入到不同行的写入。 在读取操作期间，如果在第一个读取缓冲器中发生后续读取命中，则将全行加载到第一个双重读取缓冲区中，并且将下一个完整行从主存储器检索到第二个读取缓冲区中。

公开(公告)号：WO1993022726A1

公开(公告)日：1993-11-11

申请号：PCT/US1993004006

申请日：1993-04-28

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  WUNDERLICH, Russell, J. ,  TAYLOR, Mark ,  STANCIL, Charles, J. ,  HUNSAKER, Mikal, C. ,  BELMONT, Brian, V.

IPC: G06F12/06

CPC classification number: G06F12/0653 ,  G06F12/1433

Abstract: A memory mapping and module enabling circuit for allowing logical 128 kbyte memory blocks to be defined for any location in any module connected to a memory system. A RAM is addressed by the system address lines defining 128 kbyte blocks, with the output data providing the row address strobe enable signals for a particular memory module and the address values necessary to place the 128 kbyte block within the module. Various other parameters such as write protect status and memory location are also provided by the RAM. Circuits and techniques for programming and reading the RAM are provided. The RAM is only programmed once, with modifications to the RAM-provided write protect status and memory location values being made based on write protect and relocation status information contained in a separate register.

Abstract translation: 存储器映射和模块使能电路，用于允许为连接到存储器系统的任何模块中的任何位置定义逻辑128K字节的存储器块。 RAM由定义128千字节块的系统地址线寻址，输出数据为特定存储器模块提供行地址选通使能信号，以及将128K字节块放置在模块内所需的地址值。 各种其他参数，如写保护状态和存储器位置也由RAM提供。 提供了用于编程和读取RAM的电路和技术。 RAM仅被编程一次，修改RAM提供的写保护状态和存储位置值是基于单独寄存器中包含的写保护和重定位状态信息进行的。

公开(公告)号：EP0664032A1

公开(公告)日：1995-07-26

申请号：EP93924909.0

申请日：1993-09-29

Applicant: Compaq Computer Corporation

Inventor： TAYLOR, Mark ,  CULLEY, Paul, R. ,  MELO, Maria, L. ,  TIPLEY, Roger, E.

IPC: G06F13

CPC classification number: G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：EP0664031B1

公开(公告)日：1997-01-22

申请号：EP93924899.3

申请日：1993-09-24

Applicant: Compaq Computer Corporation

Inventor： TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13/36 ,  G06F13/364

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：EP0664030B1

公开(公告)日：1999-05-12

申请号：EP93924286.3

申请日：1993-09-29

Applicant: Compaq Computer Corporation

Inventor： CULLEY, Paul, R. ,  TAYLOR, Mark

IPC: G06F12/02 ,  G06F13/40

CPC classification number: G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

公开(公告)号：EP0664031A1

公开(公告)日：1995-07-26

申请号：EP93924899.0

申请日：1993-09-24

Applicant: Compaq Computer Corporation

Inventor： TIPLEY, Roger, E. ,  MORIARTY, Michael ,  TAYLOR, Mark

IPC: G06F13

CPC classification number: G06F13/36 ,  G06F13/364

Abstract: Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of (n/2)x(n-1) priority bits monitors the relative priority between each pair of elements. An element receives the highest priority when each of the n-1 priority bits associated with that element points to it. In the arbitration scheme, the current bus master of the host bus determines when transfer of control of the host bus occurs as governed by one of the prioritization schemes. The arbitration scheme gives EISA bus masters, RAM refresh and DMA greater priority than CPUs acting as bus masters, and allows a temporary bus master to interrupt the current bus master to perform a write-back cache intervention cycle. The arbitration scheme also supports address pipelining, bursting, split transactions and reservations of CPUs aborted when attempting a locked cycle. Address pipelining allows the next bus master to assert its address and status signals before the beginning of the data transfer phase of the next bus master. Split transactions allow a CPU posting a read to the EISA bus to arbitrate the host bus to another device without re-arbitrating for the host bus to retrieve the data. The data is asserted on the host bus when it is idle even if the host bus is being controlled by another device.

公开(公告)号：EP0664030A1

公开(公告)日：1995-07-26

申请号：EP93924286.0

申请日：1993-09-29

Applicant: Compaq Computer Corporation

Inventor： CULLEY, Paul, R. ,  TAYLOR, Mark

IPC: G06F12 ,  G06F13

CPC classification number: G06F13/1673 ,  G06F12/0215 ,  G06F13/4018

Abstract: Double buffering operations to reduce host bus hold times when an expansion bus master is accessing the main memory on a host bus of a computer system. A system data buffer coupled between the main memory and the expansion bus includes 256-bit double read and write buffers. A memory controller coupled to the double read and write buffers and to the expansion bus includes primary and secondary address latches corresponding to the double buffers. The memory controller detects access to the main memory, compares the expansion bus address with the primary and secondary addresses and controls the double read and write buffers and the primary and secondary address latches accordingly. During write operations, data to be written to the same line of memory is written to a first of the double write buffers until a write occurs to an address to a different line before data is transferred to main memory. During read operations, a full line is loaded into a first of the double read buffers, and the next full line is retrieved into a second read buffer from main memory if a subsequent read hit occurs in the first read buffer.