公开(公告)号：WO1995010092A1

公开(公告)日：1995-04-13

申请号：PCT/US1994011379

申请日：1994-10-05

Applicant: NSOFT SYSTEMS, INC. ,  COMPAQ COMPUTER CORPORATION

Inventor： NSOFT SYSTEMS, INC. ,  COMPAQ COMPUTER CORPORATION ,  LEE, Ven, L. ,  DAWSON, William, M. ,  DOUD, Donald, L.

IPC: G06F17/50

CPC classification number: H01L27/11803 ,  G06F17/5068 ,  H01L27/118

Abstract: In accordance with this invention, matched performance of alternate sourced ASICs is achieved while still allowing for the smallest die size possible from each alternate source fabrication facility. In one aspect of this invention, the width of electrical interconnects (Wm1, Wm2) are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In another aspect, transistor channel widths (Wpd, Wnd) are adjusted to compensate for differences in capacitances of a given interconnect path in devices fabricated by different fabrication facilities. In yet another aspect of this invention, capacitance is added to the gates of transistors to decrease their speed, when manufactured by an inherently faster process.

Abstract translation: 根据本发明，实现了替代源ASIC的匹配性能，同时仍然允许来自每个替代源制造设施的最小管芯尺寸。 在本发明的一个方面中，电气互连的宽度（Wm1，Wm2）被调整以补偿由不同的制造设备制造的器件中给定的互连路径的电容的差异。 在另一方面，调整晶体管沟道宽度（Wpd，Wnd）以补偿由不同制造设备制造的器件中的给定互连路径的电容差。 在本发明的另一方面，当通过固有更快的工艺制造时，电容被添加到晶体管的栅极以降低它们的速度。

公开(公告)号：WO1995001611A1

公开(公告)日：1995-01-12

申请号：PCT/US1994007583

申请日：1994-06-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  SELLERS, Charles, A.

IPC: G06K11/18

CPC classification number: G06F1/1662 ,  G06F1/1616 ,  G06F1/169 ,  G06F3/0213

Abstract: A computer having a keyboard unit with a spacebar wherein a trackball module is mounted within the spacebar for ease of access by left-handed or right-handed persons. The trackball module is mounted intermediately of the spacebar. In one embodiment, the trackball module is mounted for movement with a spacebar and in another embodiment, the trackball module is stationary such that the spacebar moves upwardly and downwardly relative to the trackball module.

Abstract translation: 具有带空格键的键盘单元的计算机，其中轨迹球模块安装在空格键内，以便左手或右撇子人易于进入。 轨迹球模块安装在空格键的中间。 在一个实施例中，轨迹球模块被安装成与空格键一起移动，并且在另一个实施例中，轨迹球模块是静止的，使得空格键相对于轨迹球模块向上和向下移动。

公开(公告)号：WO1994011998A1

公开(公告)日：1994-05-26

申请号：PCT/US1993010907

申请日：1993-11-08

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  NAGEL, Paul, E. ,  CASTELL, Robin, T.

IPC: H04Q07/04

CPC classification number: H04W88/02 ,  H04M11/06 ,  Y02D70/00

Abstract: A modem (12) is incorporated into a laptop computer (10) and directly connected to either a cellular phone (22), a land line (18), or both. The modem is provided with two connectors (14, 16), one for connection with a cellular phone or external DAA (24), the other for connection to a normal land line via an internal DAA (112). The modem selectively enables either the connector for the cellular phone or external DAA, or the connector for its internal DAA. The modem defaults to selecting the cellular phone or external DAA if it is connected, and only if they are not connected selects the internal DAA. These defaults can be overridden by user commands. Further, the modem can independently power down a connected internal DAA, external DAA, or cellular phone to conserve power.

Abstract translation: 调制解调器（12）被并入到膝上型计算机（10）中并且直接连接到蜂窝电话（22），陆线（18）或两者。 调制解调器具有两个连接器（14,16），一个用于与蜂窝电话或外部DAA（24）连接，另一个用于通过内部DAA（112）连接到正常的陆线。 调制解调器选择性地启用用于蜂窝电话或外部DAA的连接器，或用于其内部DAA的连接器。 调制解调器默认选择手机或外部DAA（如果已连接），并且只有在未连接时才选择内部DAA。 这些默认值可以被用户命令覆盖。 此外，调制解调器可以独立地断开连接的内部DAA，外部DAA或蜂窝电话以节省电力。

公开(公告)号：WO1994008293A1

公开(公告)日：1994-04-14

申请号：PCT/US1993009431

申请日：1993-09-30

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  LANDRY, John, A. ,  WOLFORD, Jeff, W. ,  FRY, Walter, G. ,  TIPLEY, Roger, E.

IPC: G06F11/20

CPC classification number: G06F11/1637 ,  G06F11/1679

Abstract: A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to the respective processor. The processors on one or more CPU boards are designated as master processors, with the processors on the remaining CPU boards being designated as mirroring or slave processors. A master processor has full access to the host bus and a second, multiplexed bus for read and write cycles, whereas the slave processors are prevented from writing to any bus. The slave processors compare write data and various control signals with that generated by its respective master processor for disparities. The system includes interrupt controller synchronization logic to synchronize interrupt requests as well as timer synchronization logic to synchronize the timers in each of the master and slave CPUs to guarantee that the master and slave CPUs operate in lockstep.

Abstract translation: 一种用于在计算机系统中操作紧耦合的镜像处理器的方法和装置。 多个CPU板耦合到通常称为主机总线的处理器/存储器总线。 每个CPU板包括一个处理器以及各个处理器本地的各种端口，定时器和中断控制器逻辑。 一个或多个CPU板上的处理器被指定为主处理器，其余CPU板上的处理器被指定为镜像或从属处理器。 主处理器具有对主机总线的完全访问和用于读和写周期的第二复用总线，而从处理器被阻止写入任何总线。 从处理器将写入数据和各种控制信号与其相应的主处理器产生的差异进行比较。 该系统包括中断控制器同步逻辑，以同步中断请求以及定时器同步逻辑，以同步每个主CPU和从CPU的定时器，以保证主CPU和从CPU处于锁定状态。

公开(公告)号：WO1993017387A1

公开(公告)日：1993-09-02

申请号：PCT/US1993001548

申请日：1993-02-19

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  STEVENS, Jeffrey, C. ,  RAMSEY, Jens, K. ,  BONELLA, Randy, M. ,  KELLY, Philip, C.

IPC: G06F12/08

CPC classification number: G06F12/0835 ,  G06F12/0811 ,  G06F13/161

Abstract: A method and apparatus for reducing the snooping requirements of a cache system and for reducing latency problems in a cache system. When a snoop access occurs to the cache, and if snoop control logic determines that the previous snoop access involved the same memory location line, then the snoop control logic does not direct the cache to snoop this subsequent access. This eases the snooping burden of the cache and thus increases the efficiency of the processor working out of the cache during this time. When a multilevel cache system is implemented, the snoop control logic directs the cache to snoop certain subsequent accesses to a previously snooped line in order to prevent cache coherency problems from arising. Latency reduction logic which reduces latency problems in the snooping operation of the cache is also included. After every processor read that is transmitted beyond the cache, i.e., cache read misses, the logic gains control of the address inputs of the cache for snooping purposes. The cache no longer needs its address bus for the read cycle and thus the read operation continues unhindered. In addition, the cache is prepared for an upcoming snoop cycle.

Abstract translation: 一种用于减少缓存系统的窥探需求并减少缓存系统中的延迟问题的方法和装置。 当高速缓存发生窥探访问时，如果侦听控制逻辑确定先前的侦听访问涉及同一内存位置行，则侦听控制逻辑不会引导高速缓存窥探此后续访问。 这缓解了缓存的窥探负担，从而提高了在此期间从高速缓存中工作的处理器的效率。 当实现多级缓存系统时，监听控制逻辑引导高速缓存窥探对先前侦听行的某些后续访问，以防止出现高速缓存一致性问题。 还包括减少高速缓存的窥探操作中的延迟问题的延迟降低逻辑。 在每个超出高速缓存的处理器读取，即高速缓存读取未命中之后，逻辑增益用于高速缓存的地址输入的控制用于窥探目的。 缓存不再需要其地址总线用于读取周期，因此读取操作不受阻碍地继续。 此外，高速缓存准备好即将到来的窥探周期。

公开(公告)号：WO1993014469A1

公开(公告)日：1993-07-22

申请号：PCT/US1993000623

申请日：1993-01-13

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  ALBERS, Thomas, M. ,  EBERST, John, V. ,  FONTENOT, Darwin ,  PYRA, Richard, L. ,  WELKER, Mark, W. ,  WOOD, Paul, B. ,  BRESENHAM, Jack, E.

IPC: G06F15/72

CPC classification number: G06T11/203

Abstract: Circuitry for drawing lines includes a video memory for storing pixel data and circuitry for generating a sequence of addresses defining a line of pixels in the video memory. A first memory stores a sequence of pattern units corresponding to the generated sequence of addresses. A second memory stores a value indicating a current pattern unit. Writing circuitry writes to the video memory at a generated address responsive to a current pattern unit. A third memory stores a control value which is accessed by update circuitry for updating the second memory to indicate the next pattern unit. The update circuitry may selectively update the second memory to the sequential pattern unit or reset the second memory to a predetermined pattern unit.

Abstract translation: 用于绘制线的电路包括用于存储像素数据的视频存储器和用于产生定义视频存储器中的像素线的地址序列的电路。 第一存储器存储对应于所生成的地址序列的模式单元序列。 第二存储器存储指示当前图案单元的值。 写入电路响应于当前模式单元以产生的地址写入视频存储器。 第三存储器存储由更新电路访问的控制值，用于更新第二存储器以指示下一个模式单元。 更新电路可以选择性地将第二存储器更新为顺序模式单元或将第二存储器复位到预定模式单元。

公开(公告)号：WO1996041306A1

公开(公告)日：1996-12-19

申请号：PCT/US1996010379

申请日：1996-06-05

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  KNOX, Richard, M. ,  MASTERS, John, R. ,  CLANCY, Kevin, F.

IPC: G06K11/08

CPC classification number: G06F3/0423 ,  G06F3/0213

Abstract: A method of determining an object's position and associated apparatus provides positional information in a form that may be conveniently communicated to a computer to calculate the object's position. In a preferred embodiment, representatively incorporated in a computer keyboard, a method of determining an object's position includes forming an optical grid of reflected beacons and detecting an obstruction of the reflected beacons. A preferred embodiment apparatus utilizes a single light source to detect an object's position in two dimensions.

Abstract translation: 确定对象的位置和相关联的装置的方法提供可以方便地传送到计算机以计算对象的位置的形式的位置信息。 在代表性地并入计算机键盘的优选实施例中，确定对象位置的方法包括形成反射信标的光栅并检测反射信标的阻塞。 优选的实施例装置利用单个光源在二维中检测物体的位置。

公开(公告)号：WO1994027827A1

公开(公告)日：1994-12-08

申请号：PCT/US1994005455

申请日：1994-05-13

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  FUSTING, Daniel, R. ,  PIES, John, R. ,  WALLACE, David, B. ,  HAYES, Donald, J.

IPC: B41J02/21

CPC classification number: B41J2/1632 ,  B41J2/14209 ,  B41J2/15 ,  B41J2/155 ,  B41J2/1609 ,  B41J2/1618 ,  B41J2/1623 ,  B41J2/2103 ,  B41J2002/14379

Abstract: An integrated multi-color drop-on-demand type ink jet printhead (12). The printhead includes a main body portion (14) and a plurality of generally parallel, longitudinally extending ink-carrying channels (36) arranged into at least two channel arrays (35a-35d). A manifold (21a-21d) corresponding to each of the at least two channel arrays and in communication with each of the ink-carrying channels (36) of the corresponding array is formed in the main body portion (14). Ink is supplied to each of the at least two channel arrays from a corresponding ink source (18a-18d), each of which is filled with a different color of ink.

Abstract translation: 一种集成的多色按需喷墨打印头（12）。 打印头包括主体部分（14）和布置在至少两个通道阵列（35a-35d）中的多个大致平行的，纵向延伸的油墨承载通道（36）。 对应于至少两个通道阵列中的每一个并且与相应阵列的每个墨水输送通道（36）连通的歧管（21a-21d）形成在主体部分（14）中。 油墨从相应的油墨源（18a-18d）供应到至少两个通道阵列中的每一个，每个油墨源都填充有不同颜色的油墨。

公开(公告)号：WO1994027825A1

公开(公告)日：1994-12-08

申请号：PCT/US1994005519

申请日：1994-05-13

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  HAYES, Donald, J. ,  STORTZ, James, L.

IPC: B41J02/16

CPC classification number: B41J2/1609 ,  B41J2/14209 ,  B41J2/1623 ,  B41J2/1632 ,  B41J2/1643 ,  Y10T29/42 ,  Y10T29/49401

Abstract: A single side interconnectable ink jet printhead and an associated method for manufacturing the same. The ink jet printhead includes a lower body portion (14) having a plurality of conductive sections (16) mounted to a top side (14a) of the lower body portion (14) and a corresponding plurality of conductive pins (20) projecting from a bottom side (14b) of the lower body portion (14). Each of the conductive sections (16) is electrically connected to the corresponding one of the conductive pins (10). A bottom side surface of each one of a plurality of generally parallel, longitudinally extending first intermediate body portions each formed of an active piezoelectric material poled in a first direction parallel to the top side surface of the lower body portion is conductively mounted to a portion of the top side surface of the lower body portion. A bottom side surface of each one of a plurality of generally parallel, longitudinally extending second intermediate body portions, each formed of an active piezoelectric material poled in a second direction opposite the first direction is conductively mounted to a top side surface of a corresponding one of the first intermediate body portions and a bottom side surface of an insulative upper body portion is conductively mounted to a top side surface of each of the plurality of second intermediate body portions.

Abstract translation: 单面可互连喷墨打印头及其制造方法。 喷墨打印头包括下主体部分（14），其具有安装到下主体部分（14）的顶侧（14a）的多个导电部分（16）和相应的多个导电部分（20） 下主体部分（14）的底侧（14b）。 每个导电部分（16）电连接到对应的一个导电引脚（10）。 多个大致平行的纵向延伸的第一中间体的每一个的底侧表面各自由平行于下主体部分的顶侧表面的第一方向极化的有源压电材料形成，导电地安装到 下主体部分的顶侧表面。 多个大致平行的纵向延伸的第二中间体部分中的每一个的底侧表面各自由与第一方向相反的第二方向极化的有源压电材料导电地安装到相应的一个的顶侧表面 绝缘上部主体部分的第一中间体部分和底侧表面被导电地安装到多个第二中间体部分的每一个的顶侧表面上。

公开(公告)号：WO1994027824A1

公开(公告)日：1994-12-08

申请号：PCT/US1994005509

申请日：1994-05-13

Applicant: COMPAQ COMPUTER CORPORATION

Inventor： COMPAQ COMPUTER CORPORATION ,  HAYES, Donald, J. ,  PIES, John, R. ,  WALLACE, David, B.

IPC: B41J02/045

CPC classification number: B41J2/1632 ,  B41J2/14209 ,  B41J2/155 ,  B41J2/1609 ,  B41J2/1618 ,  B41J2/1623

Abstract: The operation of U or UU type drop-on-demand ink jet printheads are enhanced by selectively incorporating therein volume modifying tapers in the ink carrying channels, means for electrically isolating portions of the actuators thereof, and/or forming a variable layer of conductive material between the upper and lower sidewall portions therefor.

Abstract translation: U或UU型按需喷墨打印头的操作通过选择性地将其中的油墨传送通道中的体积改变锥度，用于电隔离其致动器的部分的装置和/或形成导电材料的可变层来增强 在其上侧壁部分和下侧壁部分之间。