公开(公告)号：US20120279772A1

公开(公告)日：2012-11-08

申请号：US13162547

申请日：2011-06-16

Applicant: Shih-Hao Sun ,  Chang-Fu Chen

Inventor： Shih-Hao Sun ,  Chang-Fu Chen

IPC: H05K1/18 ,  H05K3/00

CPC classification number: H01L21/563 ,  H01L21/4821 ,  H01L21/568 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.

Abstract translation: 提供一种封装结构的制造方法。 在制造方法中，提供具有种子层的金属基板。 在种子层的一部分上形成图案化电路层。 第一图案化的干膜层形成在种子层的另一部分上。 使用第一图案化干膜层作为电镀掩模，在图案化电路层上电镀表面处理层。 去除第一图案干膜层。 执行芯片接合工艺以将芯片电连接到表面处理层。 在金属基板上形成密封剂。 密封剂封装芯片，表面处理层和图案化电路层。 除去金属基底和种子层以露出密封剂的底表面和图案化电路层的下表面。

公开(公告)号：US20090294401A1

公开(公告)日：2009-12-03

申请号：US12129689

申请日：2008-05-30

Applicant: Chang-Fu Chen

Inventor： Chang-Fu Chen

IPC: H01B13/00

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/81136 ,  H01L2224/81801 ,  H05K3/06 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4652 ,  H05K3/4682 ,  H05K2201/0361 ,  H05K2201/0367 ,  H05K2203/0353 ,  H05K2203/0384 ,  Y10T29/49155 ,  Y10T29/49169

Abstract: A method of fabricating a packaging substrate is disclosed. A cladding sheet comprised of a first metal foil, a second metal foil and an etch stop layer interposed between the first and second metal foils is provided. The first metal foil is then patterned into a first circuit trace. An insulating layer is laminated onto the first circuit trace. Thereafter, the second metal foil is patterned into a plurality of bump pads. The etch stop layer that is not covered by the bump pads is stripped off. A solder mask is applied to fill the spacing between the bump pads. A top surface of each of the bump pads is etched to form a bonding aperture in a self-aligned fashion.

Abstract translation: 公开了一种制造封装衬底的方法。 提供由第一金属箔，第二金属箔和介于第一和第二金属箔之间的蚀刻停止层构成的覆层片。 然后将第一金属箔图案化成第一电路迹线。 绝缘层被层压到第一电路迹线上。 此后，将第二金属箔图案化成多个凸块焊盘。 剥离不被凸块焊接的蚀刻停止层被剥离。 施加焊接掩模以填充凸块之间的间隔。 每个凸块焊盘的顶表面被蚀刻以自对准的方式形成接合孔。

公开(公告)号：US20050205990A1

公开(公告)日：2005-09-22

申请号：US10946929

申请日：2004-09-21

Applicant: C. F. Wang ,  Chang-Fu Chen

Inventor： C. F. Wang ,  Chang-Fu Chen

IPC: H01L23/04 ,  H01L23/498 ,  H01L23/50 ,  H05K1/00

CPC classification number: H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48233 ,  H01L2224/4912 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated circuit carrier with conductive rings and a semiconductor device integrated with the carrier are proposed. A plurality of concave structures are formed on the conductive rings at predetermined positions above which a plurality of wires traverse, the wires being provided for electrically connecting the carrier to a semiconductor chip mounted on the carrier. Therefore, an insulating effect between the wires and the conductive rings is provided to prevent short circuit, so as to maintain the performance of the semiconductor device.

Abstract translation: 提出了一种具有导电环的集成电路载体和与载体集成的半导体器件。 在导电环上形成多个凹形结构，该预定位置在多个电线穿过其上方的预定位置处，所述导线被设置用于将载体电连接到安装在载体上的半导体芯片。 因此，提供导线与导电环之间的绝缘效果以防止短路，从而保持半导体器件的性能。

公开(公告)号：US06437447B1

公开(公告)日：2002-08-20

申请号：US09697296

申请日：2000-10-27

Applicant: Chien-Ping Huang ,  Chin-Yuan Hung ,  Chang-Fu Chen ,  Jenn-Shyh Yu ,  Jui-Hsiang Hung

Inventor： Chien-Ping Huang ,  Chin-Yuan Hung ,  Chang-Fu Chen ,  Jenn-Shyh Yu ,  Jui-Hsiang Hung

IPC: H01L2348

CPC classification number: H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: In a dual-sided chip package without a die pad according to the invention, a first die can be fixed directly on the lead fingers of a leadframe, a support bar, or bus bars, while a second die is attached to the first die. Without a die pad, the distance between the surfaces of the dies and the plastic surface of the package therefore gets longer. Thus, the invention enables a large decrease in the probability of generating voids in the plastic and there is no need to grind the dies. Besides, it improves the vibration and floating characteristics of the dies in the manufacturing process and thus prevents the exposure of the bonding wires and the shelling off or breaking of the dies. The invention can raise the yield of chip packages.

Abstract translation: 在根据本发明的没有芯片焊盘的双面芯片封装中，第一裸片可以直接固定在引线框架，支撑杆或汇流条的引线上，而第二裸片附接到第一裸片。 没有管芯焊盘，因此，模具表面与封装的塑料表面之间的距离变长。 因此，本发明能够大大降低在塑料中产生空隙的可能性，并且不需要研磨模具。 此外，在制造过程中，提高了模具的振动和浮动特性，防止了接合线的暴露和模具脱壳或断裂。 本发明可以提高芯片封装的产量。