公开(公告)号：US6062820A

公开(公告)日：2000-05-16

申请号：US201707

申请日：1998-12-01

Applicant: Chun-Ming Wang

Inventor： Chun-Ming Wang

IPC: F04D25/08 ,  F04D29/34 ,  B63H1/20

CPC classification number: F04D25/088 ,  F04D29/34

Abstract: An improvement in the structure for mounting blades of a ceiling fan, characterized in that a motor comprising a bottom formed with a plurality of threaded holes, an annular ring-like mounting secured to the bottom of the electric motor by screws and provided with a plurality of brackets each having a groove which gradually decreases in size from an upper portion toward an lower portion thereof, each of the blades provided with a rod having a tongue which gradually decreases in size from an upper end to an lower end thereof, the tongue being configured so that the upper end of the tongue has same size of the upper portion of the groove while the lower end of the tongue has same size of the lower portion of the groove thereby enabling the tongue to fit into the groove but not slide out thereof.

Abstract translation: 一种用于安装吊扇的结构的改进，其特征在于，电动机包括形成有多个螺纹孔的底部，环形环状安装件，通过螺钉固定在电动机的底部并且设置有多个 每个叶片具有从上部向下部逐渐减小的凹槽，每个叶片设置有具有从上端到下端逐渐减小的舌部的杆，舌部是 使得舌头的上端具有相同尺寸的槽的上部，而舌的下端具有相同尺寸的槽的下部，从而使得舌可以装配到槽中但不滑出 。

公开(公告)号：US08394656B2

公开(公告)日：2013-03-12

申请号：US12831898

申请日：2010-07-07

Applicant: Chun-Ming Wang ,  Jeffrey Lan ,  Teruo Sasagawa

Inventor： Chun-Ming Wang ,  Jeffrey Lan ,  Teruo Sasagawa

IPC: H01L21/00

CPC classification number: B81C1/00047 ,  B81B2201/047 ,  B81C2201/0108 ,  B81C2201/0111 ,  G02B26/001

Abstract: MEMS devices (such as interferometric modulators) may be fabricated using a sacrificial layer that contains a heat vaporizable polymer to form a gap between a moveable layer and a substrate. One embodiment provides a method of making a MEMS device that includes depositing a polymer layer over a substrate, forming an electrically conductive layer over the polymer layer, and vaporizing at least a portion of the polymer layer to form a cavity between the substrate and the electrically conductive layer. Another embodiment provides a method for making an interferometric modulator that includes providing a substrate, depositing a first electrically conductive material over at least a portion of the substrate, depositing a sacrificial material over at least a portion of the first electrically conductive material, depositing an insulator over the substrate and adjacent to the sacrificial material to form a support structure, and depositing a second electrically conductive material over at least a portion of the sacrificial material, the sacrificial material being removable by heat-vaporization to thereby form a cavity between the first electrically conductive layer and the second electrically conductive layer.

Abstract translation: 可以使用包含热可汽化聚合物以在可移动层和基底之间形成间隙的牺牲层来制造MEMS器件（例如干涉式调制器）。 一个实施例提供了一种制造MEMS器件的方法，该MEMS器件包括在衬底上沉积聚合物层，在聚合物层上形成导电层，并蒸发聚合物层的至少一部分以在衬底和电 导电层。 另一个实施例提供了制造干涉式调制器的方法，该方法包括提供衬底，在衬底的至少一部分上沉积第一导电材料，在第一导电材料的至少一部分上沉积牺牲材料，沉积绝缘体 在所述衬底上并且邻近所述牺牲材料以形成支撑结构，以及在所述牺牲材料的至少一部分上沉积第二导电材料，所述牺牲材料可通过热蒸发而被去除，从而在所述第一电 导电层和第二导电层。

公开(公告)号：US08149497B2

公开(公告)日：2012-04-03

申请号：US12711594

申请日：2010-02-24

Applicant: Teruo Sasagawa ,  Clarence Chui ,  Manish Kothari ,  SuryaPrakash Ganti ,  Jeffrey B. Sampsell ,  Chun-Ming Wang

Inventor： Teruo Sasagawa ,  Clarence Chui ,  Manish Kothari ,  SuryaPrakash Ganti ,  Jeffrey B. Sampsell ,  Chun-Ming Wang

IPC: G02B26/00

CPC classification number: G02B26/0841 ,  B81B2201/042 ,  B81B2203/0307 ,  B81C1/00595 ,  B81C2201/014 ,  G02B26/001

Abstract: A microelectromechanical systems device having support structures formed of sacrificial material surrounded by a protective material. The microelectromechanical systems device includes a substrate having an electrode formed thereon. Another electrode is separated from the first electrode by a cavity and forms a movable layer, which is supported by support structures formed of a sacrificial material.

公开(公告)号：US20100330806A1

公开(公告)日：2010-12-30

申请号：US12458017

申请日：2009-06-29

Applicant: Chun-Ming Wang ,  Chenche Huang ,  Masaaki Higashitani

Inventor： Chun-Ming Wang ,  Chenche Huang ,  Masaaki Higashitani

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/31144

Abstract: One embodiment of the invention provides a method of forming a plurality of contact holes, including forming a first feature and a second feature over an underlying material, forming sidewall spacers on the first and second features, removing the first and second features without removing the sidewall spacers, forming a cover mask at least partially exposing the sidewall spacers, and etching the underlying material using the cover mask and the sidewall spacers as a mask to form the plurality of contact holes.

Abstract translation: 本发明的一个实施例提供一种形成多个接触孔的方法，包括在下面的材料上形成第一特征和第二特征，在第一和第二特征上形成侧壁间隔物，去除第一和第二特征而不移除侧壁 间隔件，形成至少部分地暴露侧壁间隔物的覆盖掩模，以及使用覆盖掩模和侧壁间隔物作为掩模蚀刻下面的材料以形成多个接触孔。

公开(公告)号：US07846756B2

公开(公告)日：2010-12-07

申请号：US12318590

申请日：2008-12-31

Applicant: Bing K. Yen ,  Chun-Ming Wang ,  Yung-Tin Chen ,  Steven Maxwell

Inventor： Bing K. Yen ,  Chun-Ming Wang ,  Yung-Tin Chen ,  Steven Maxwell

IPC: H01L21/00

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/3086 ,  H01L27/101 ,  H01L27/1021

Abstract: A method of making a device is disclosed including: forming a first hard mask layer over an underlying layer; forming a first imprint resist layer over the underlying layer; forming first features over the first hard mask layer by bringing a first imprint template in contact with the first imprint resist layer; forming a first spacer layer over the first features; etching the first spacer layer to form a first spacer pattern and to expose top of the first features; removing the first features; patterning the first hard mask, using the first spacer pattern as a mask, to form first hard mask features; and etching at least part of the underlying layer using the first hard mask features as a mask.

Abstract translation: 公开了一种制造器件的方法，包括：在下层上形成第一硬掩模层; 在所述下层上形成第一印记抗蚀剂层; 通过使第一印模模板与第一印模抗蚀剂层接触而在第一硬掩模层上形成第一特征; 在所述第一特征上形成第一间隔层; 蚀刻第一间隔层以形成第一间隔图案并暴露第一特征的顶部; 去除第一个特征; 使用第一间隔图案作为掩模来图案化第一硬掩模以形成第一硬掩模特征; 并使用第一硬掩模特征作为掩模蚀刻至少部分下层。

公开(公告)号：US07704773B2

公开(公告)日：2010-04-27

申请号：US11506600

申请日：2006-08-18

Applicant: Lior Kogut ,  Chengbin Qiu ,  Chun-Ming Wang ,  Stephen Zee ,  Fan Zhong

Inventor： Lior Kogut ,  Chengbin Qiu ,  Chun-Ming Wang ,  Stephen Zee ,  Fan Zhong

IPC: H01L21/00

CPC classification number: G02B26/0841 ,  B81B3/0072 ,  B81B2201/047 ,  B81B2203/0163 ,  B81B2203/019 ,  B81B2203/0307 ,  B81B2203/053 ,  B81C1/00142 ,  B81C1/00666 ,  B81C2201/0167 ,  G02B26/001 ,  Y10S359/90

Abstract: Embodiments of MEMS devices include support structures having substantially vertical sidewalls. Certain support structures are formed through deposition of self-planarizing materials or via a plating process. Other support structures are formed via a spacer etch. Other MEMS devices include support structures at least partially underlying a movable layer, where the portions of the support structures underlying the movable layer include a convex sidewall. In further embodiments, a portion of the support structure extends through an aperture in the movable layer and over at least a portion of the movable layer.

Abstract translation: MEMS器件的实施例包括具有基本垂直侧壁的支撑结构。 通过沉积自平面化材料或通过电镀工艺形成某些支撑结构。 通过间隔物蚀刻形成其它支撑结构。 其它MEMS器件包括至少部分在可移动层下方的支撑结构，其中可移动层下面的支撑结构的部分包括凸形侧壁。 在另外的实施例中，支撑结构的一部分延伸穿过可移动层中的孔并且在可移动层的至少一部分上方延伸。

公开(公告)号：US20090321789A1

公开(公告)日：2009-12-31

申请号：US12216109

申请日：2008-06-30

Applicant: Chun-Ming Wang ,  Yung-Tin Chen ,  Roy E. Scheuerlein

Inventor： Chun-Ming Wang ,  Yung-Tin Chen ,  Roy E. Scheuerlein

IPC: H01L21/822 ,  H01L27/10

CPC classification number: H01L27/101 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/32139 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: A method of making a semiconductor device includes forming at least one device layer over a substrate, forming a plurality of spaced apart first features over the device layer, where each three adjacent first features form an equilateral triangle, forming sidewall spacers on the first features, filling a space between the sidewall spacers with a plurality of filler features, selectively removing the sidewall spacers, and etching the at least one device layer using at least the plurality of filler features as a mask. A device contains a plurality of bottom electrodes located over a substrate, a plurality of spaced apart pillars over the plurality of bottom electrodes, and a plurality of upper electrodes contacting the plurality of pillars. Each three adjacent pillars form an equilateral triangle, and each pillar comprises a semiconductor device. The plurality of pillars include a plurality of first pillars having a first shape and a plurality of second pillars having a second shape different from the first shape.

Abstract translation: 制造半导体器件的方法包括在衬底上形成至少一个器件层，在器件层上形成多个间隔开的第一特征，其中每三个相邻的第一特征形成等边三角形，在第一特征上形成侧壁间隔物， 用多个填料特征填充侧壁间隔件之间的空间，选择性地去除侧壁间隔物，以及使用至少多个填料特征作为掩模蚀刻至少一个器件层。 一种器件包含位于衬底上方的多个底部电极，多个底部电极上的多个间隔开的支柱以及与多个支柱接触的多个上部电极。 每三个相邻的柱形成等边三角形，每个柱包括半导体器件。 多个支柱包括具有第一形状的多个第一支柱和具有不同于第一形状的第二形状的多个第二支柱。

公开(公告)号：US20090257105A1

公开(公告)日：2009-10-15

申请号：US12101073

申请日：2008-04-10

Applicant: Gang Xu ,  Chun-Ming Wang ,  Fan Zhong ,  Qi Luo

Inventor： Gang Xu ,  Chun-Ming Wang ,  Fan Zhong ,  Qi Luo

IPC: G02B26/00

CPC classification number: G02B5/003 ,  G02B5/201 ,  G02B26/001

Abstract: A thin black mask is created using a single mask process. A dielectric layer is deposited over a substrate. An absorber layer is deposited over the dielectric layer and a reflector layer is deposited over the absorber layer. The absorber layer and the reflector layer are patterned using a single mask process.

Abstract translation: 使用单个掩码进程创建一个细黑色掩模。 介电层沉积在衬底上。 在电介质层上沉积吸收层，在吸收层上沉积反射层。 使用单个掩模工艺对吸收层和反射层进行构图。

公开(公告)号：US20050074964A1

公开(公告)日：2005-04-07

申请号：US10707112

申请日：2003-11-21

Applicant: Ming-Hung Lo ,  Liang-Pin Chou ,  Chun-Ming Wang ,  Li-Fu Chen

Inventor： Ming-Hung Lo ,  Liang-Pin Chou ,  Chun-Ming Wang ,  Li-Fu Chen

IPC: H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76832

Abstract: A method of fabricating a passivation layer is provided. A substrate with a plurality of device structures and at least an interconnect thereon is provided. A patterned metallic layer is formed over the interconnection layer. A plasma-enhanced chemical vapor deposition process is performed to form a first passivation over the metallic layer such that the processing pressure is higher (and/or the processing power is lower) than the pressure (the power) used in prior art. A moisture impermeable second passivation is formed over the first passivation layer. With the first passivation formed in a higher processing pressure (and/or lower processing power), damages to metallic layers or devices due to plasma bombardment is minimized.

Abstract translation: 提供一种制造钝化层的方法。 提供具有多个器件结构并且至少在其上的互连的衬底。 在互连层上形成图案化的金属层。 执行等离子体增强化学气相沉积工艺以在金属层上形成第一钝化，使得处理压力比现有技术中使用的压力（功率）更高（和/或处理能力较低）。 在第一钝化层上形成不透水的第二钝化。 由于在较高的处理压力（和/或较低的处理能力）下形成的第一钝化，由于等离子体轰击而对金属层或器件造成的损害最小化。

公开(公告)号：US08325529B2

公开(公告)日：2012-12-04

申请号：US12813437

申请日：2010-06-10

Applicant: Chen-Che Huang ,  Chun-Ming Wang ,  Masaaki Higashitani

Inventor： Chen-Che Huang ,  Chun-Ming Wang ,  Masaaki Higashitani

IPC: G11C16/04

CPC classification number: H01L27/11551 ,  G11C16/0483 ,  H01L23/485 ,  H01L27/11519 ,  H01L27/11556 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Bit line connections for non-volatile storage devices and methods for fabricating the same are disclosed. At least two different types of bit line connections may be used between memory cells and bit lines. The different types of bit line connections may be structurally different from each other as follows. One type of bit line connection may include a metal pad between an upper via and lower via. Another type of bit line connection may include an upper via and lower via, but does not include the metal pad. Three rows of bit line connections may be used to relax the pitch. For example, two rows of bit line connections on the outside may have the metal pad, whereas bit line connections in the middle row do not have the metal pad.

Abstract translation: 公开了用于非易失性存储装置的位线连接及其制造方法。 可以在存储器单元和位线之间使用至少两种不同类型的位线连接。 不同类型的位线连接可以在结构上彼此不同，如下所述。 一种类型的位线连接可以包括在上通孔和下通孔之间的金属垫。 另一种类型的位线连接可以包括上通孔和下通孔，但不包括金属垫。 可以使用三排位线连接来放松间距。 例如，外部的两行位线连接可以具有金属焊盘，而中间行中的位线连接不具有金属焊盘。