公开(公告)号：EP2204843A2

公开(公告)日：2010-07-07

申请号：EP10160546.7

申请日：2003-08-01

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi ,  Ikeda, Masanobu ,  Kimura, Takahiro

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L27/04 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L21/76838 ,  H01L23/5329 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05546 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/13091 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2924/01004

Abstract: In a pad forming region electrically connecting an element forming region to the outside, in which a low dielectric constant insulating film is formed in association with in the element forming region, a Cu film serving as a via formed in the low dielectric constant insulating film in the pad forming region is disposed in higher density than that of a Cu film serving as a via in the element forming region. Hereby, when an internal stress occurs, the stress is prevented from disproportionately concentrating on the via, and deterioration of a function of a wiring caused thereby can be avoided.

Abstract translation: 在与元件形成区域相关联地形成有低介电常数绝缘膜的元件形成区域与外部电连接的焊盘形成区域中，形成在低介电常数绝缘膜中的通孔的Cu膜 衬垫形成区域以比用作元件形成区域中的通路的Cu膜的密度高的方式设置。 因此，当发生内部应力时，防止应力不成比例地集中在通孔上，并且可以避免由此引起的布线的功能的劣化。

公开(公告)号：EP2175486A2

公开(公告)日：2010-04-14

申请号：EP10000803.6

申请日：2003-07-24

Applicant: Fujitsu Microelectronics Limited

Inventor： Watanabe, Kenichi

IPC: H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective fil ling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此，能够防止埋入导体的缺陷，能够防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。