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公开(公告)号：WO2017116524A1
公开(公告)日：2017-07-06
申请号：PCT/US2016/055555
申请日：2016-10-05
Applicant: GENERAL ELECTRIC COMPANY
Inventor： JACOB, Biju , VAFI, Habib , YANOFF, Brian David , SHAW, Jeffery Jon , GUO, Jianjun
IPC: H01L27/146
CPC classification number: H01L27/14689 , G01T1/2018 , G01T1/247 , H01L27/14625 , H01L27/14636 , H01L27/14658 , H01L27/14661 , H01L27/14663 , H01L27/1469
Abstract: Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.
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12.发明申请DIGITAL READOUT ARCHITECTURE FOR FOUR SIDE BUTTABLE DIGITAL X-RAY DETECTOR 审中-公开数字读取架构，用于四边可插入式数字X射线探测器
公开(公告)号：WO2017074610A1
公开(公告)日：2017-05-04
申请号：PCT/US2016/053029
申请日：2016-09-22
Applicant: GENERAL ELECTRIC COMPANY
Inventor： KOUADA, Ibrahim Issoufou , YANOFF, Brian David , SHORT, Jonathan David , GUO, Jianjun , JACOB, Biju
IPC: H04N5/341 , H04N5/3745 , H04N5/32
CPC classification number: G01T1/247 , H01L27/14641 , H04N5/32 , H04N5/3415 , H04N5/37455 , H04N5/37457
Abstract: An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines - selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.
Abstract translation: 包括具有片上数字化电子读出电路的四侧可对子成像器像素阵列的成像器片。 从多个成像器中形成像素分组。 包括用于每个像素分组的缓冲放大器的读出电子器件连接到可对齐的成像器的相应输出。 共享模拟前端连接到像素分组的各个缓冲放大器。 相对于共享模拟前端的公共中心位置处的模数转换器包括三条数据线 - 选择输入/输出线以单独选择输出，时钟输入线和共享数字输出线。 从各个缓冲放大器输出的像素可通过在选择输入/输出线上提供的数据来寻址，并且像素输出被提供在共享数字输出线上。 连接到可编程逻辑器件的I / O线，成像器串行数据输入作为大规模并行数据流输出。
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13.发明申请
公开(公告)号：WO2010024967A1
公开(公告)日：2010-03-04
申请号：PCT/US2009/048853
申请日：2009-06-26
Applicant: GENERAL ELECTRIC COMPANY , RAO, Naresh, Kesavan , YANOFF, Brian, David , DU, Yanfeng , GUO, Jianjun
Inventor： RAO, Naresh, Kesavan , YANOFF, Brian, David , DU, Yanfeng , GUO, Jianjun
IPC: G01T1/17
Abstract: An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration parameter for the circuitry, and a channel-select register configured to identify a channel of the plurality of channels to be configured. The ASIC further includes a configuration-select register configured to identify the programmable register to be used for channel configuration, and a communications interface configured to transmit instructions received from a controller to one of the channel-select register, the configuration-select register, and the plurality of programmable registers.
Abstract translation: 一种专用集成电路（ASIC），包括多个通道，每个通道具有用于时间和能量鉴别的电路，多个可编程寄存器，每个可编程寄存器被配置为输出用于该电路的至少一个配置参数， 选择寄存器，其被配置为识别要配置的多个信道的信道。 该ASIC还包括一配置选择寄存器，该配置选择寄存器被配置为识别要用于信道配置的可编程寄存器;以及通信接口，被配置为将从控制器接收的指令发送到频道选择寄存器，配置选择寄存器和 多个可编程寄存器。
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Patent Agency Ranking
公开(公告)号：EP3234648A1
公开(公告)日：2017-10-25
申请号：EP15774802.1
申请日：2015-09-18
Applicant: General Electric Company
Inventor： GUO, Jianjun , DOLINSKY, Sergei Ivanovich
CPC classification number: H04N17/002 , G01T1/2018 , G01T1/208 , G01T1/248 , H04N5/341
Abstract: A silicon photomultiplier includes a plurality of microcells providing a pulse output in response to an incident radiation, each microcell including circuitry configured to enable and disable the pulse output. Each microcell includes a cell disable switch. The control logic circuit controls the cell disable switch and a self-test circuit. A microcell's pulse output is disabled when the cell disable switch is in a first state. A method for self-test calibration of microcells includes providing a test enable signal to the microcells, integrating dark current for a predetermined time period, comparing the integrated dark current to a predetermined threshold level, and providing a signal if above the predetermined threshold level.
Abstract translation: 硅光电倍增管包括响应于入射辐射而提供脉冲输出的多个微单元，每个微单元包括被配置为启用和禁用脉冲输出的电路。 每个微蜂窝包括一个蜂窝禁用开关。 控制逻辑电路控制单元禁用开关和自测电路。 当单元禁用开关处于第一状态时，微单元的脉冲输出被禁用。 用于微单元的自测校准的方法包括向微单元提供测试使能信号，将暗电流积分预定的时间段，将积分的暗电流与预定阈值电平进行比较，并且如果高于预定阈值电平则提供信号。
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公开(公告)号：EP3369247A1
公开(公告)日：2018-09-05
申请号：EP16782329.3
申请日：2016-09-22
Applicant: General Electric Company
Inventor： KOUADA, Ibrahim Issoufou , YANOFF, Brian David , SHORT, Jonathan David , GUO, Jianjun , JACOB, Biju
IPC: H04N5/341 , H04N5/3745 , H04N5/32
CPC classification number: G01T1/247 , H01L27/14641 , H04N5/32 , H04N5/3415 , H04N5/37455 , H04N5/37457
Abstract: An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines—selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.
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公开(公告)号：EP3071995A1
公开(公告)日：2016-09-28
申请号：EP14761447.3
申请日：2014-08-12
Applicant: General Electric Company
Inventor： DOLINSKY, Sergei , GUO, Jianjun
IPC: G01T1/24
CPC classification number: G01T1/248 , G01J1/44 , G01J2001/4466 , G01T1/2006 , G01T1/208 , G01T1/247 , G01T1/249 , H01L31/102 , H01L31/115
Abstract: Photomultipliers are disclosed which comprise circuitry for detecting photo electric events and generating short digital pulses in response. In one embodiment, the photomultipliers comprise solid state photomultipliers having an array of microcells. The microcells, in one embodiment, in response to incident photons, generate a digital pulse signal having a duration of about 2 ns or less.
Abstract translation: 公开了光电倍增管，其包括用于检测光电事件并响应产生短数字脉冲（110）的电路。 在一个实施例中，光电倍增管包括具有微单元阵列（46）的固态光电倍增器（40）。 在一个实施例中，微单元（46）响应于入射光子而生成具有约2ns或更短持续时间的数字脉冲信号（110）。
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公开(公告)号：EP3634234A1
公开(公告)日：2020-04-15
申请号：EP18727118.4
申请日：2018-05-07
Applicant: General Electric Company
Inventor： RUI, Xue , FU, Geng , JIN, Yannan , GUO, Jianjun , EDIC, Peter Michael , YANOFF, Brian David
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公开(公告)号：EP3596511A1
公开(公告)日：2020-01-22
申请号：EP18701909.6
申请日：2018-01-11
Applicant: General Electric Company
Inventor： FU, Geng , RUI, Xue , JIN, Yannan , GUO, Jianjun , EDIC, Peter Michael , YANOFF, Brian David
IPC: G01T1/24
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