Abstract:
Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.
Abstract:
The present approach relates to scatter correction of signals acquired using radiation detectors on a pixel-by-pixel basis. In certain implementations, the systems and methods disclosed herein facilitate scatter correction for signals generated using a detector having segmented detector elements, such as may be present in an energy-resolving, photon-counting CT imaging system.
Abstract:
The present approach relates to the use of detector elements (i.e., reference detector pixels) positioned under septa of an anti-scatter collimator. Signals detected by the reference detector pixels may be used to correct for charging-sharing events with adjacent pixels and/or to characterize or correct for focal spot misalignment either in real time or as a calibration step.
Abstract:
The present approach relates to the use of reference pixels provided between the primary pixels of a detector panel. Coincidence circuitry or logic may be employed so that the measured signal arising from the same X-ray event may be properly, that is the signal measured at both a reference and primary pixel may be combined so as to provide an accurate estimate of the measured signal, at an appropriate location on the detector panel.
Abstract:
There is provided an x-ray detector (20) having a number of x-ray detector sub- modules (21-1, 21-2). Each detector sub-module (21) is an edge-on detector sub- module having an array of detector elements (22) extending in at least two directions, wherein one of the directions has a component in the direction of incoming x-rays. The detector sub-modules (21) are stacked one after the other and/or arranged side- by-side. For at least part of the detector sub-modules (21), the detector sub-modules (21) are arranged for providing a gap between adjacent detector sub-modules (21-1, 21-2), where at least part of the gap is not directed linearly towards the x-ray focal point of an x-ray source.
Abstract:
The present approach relates to self-calibration of CT detectors based on detected misalignment of the detector and X-ray source. The present approach make the detector more robust to changes against temperature and focal spot movements. The diagnostic image generated by energy resolving calibrated response signals is able to present enhanced features compared to conventional CT based diagnostic images.
Abstract:
Various approaches are discussed for using four-side buttable CMOS tiles to fabricate detector panels, including large-area detector panels. Fabrication may utilize pads and interconnect structures formed on the top or bottom of the CMOS tiles. Electrical connection and readout may utilize readout and digitization circuitry provided on the CMOS tiles themselves such that readout of groups or sub-arrays of pixels occurs at the tile level, while tiles are then readout at the detector level such that readout operations are tiered or multi-level.
Abstract:
An imager tile including four-side buttable sub-imager pixel arrays with on-chip digitizing electronic readout circuit. Pixel groupings formed from among the plurality of imagers. Readout electronics including a buffer amplifier for each of the pixel groupings are connected to respective outputs of buttable imagers. Shared analog front ends connect to respective buffer amplifiers of pixel groupings. An analog-to-digital converter at a common centroid location relative to the shared analog front ends includes three data lines - selection input/output line to individually select an output, a clock input line, and a shared digital output line. A pixel output from a respective buffer amplifier is addressable by data provided on the selection input/output line, and the pixel output is provided on the shared digital output line. The I/O lines connected to a programmable logic device where the imager serial data input is output as a massively parallel data stream.
Abstract:
The present disclosure relates to fabrication and use of a phase-contrast imaging detector that includes sub-pixel resolution electrodes or photodiodes spaced to correspond to a phase-contrast interference pattern. A system using such a detector may employ fewer gratings than are typically used in a phase-contrast imaging system, with certain functionality typically provided by a detector-side analyzer grating being performed by sub-pixel resolution structures (e.g., electrodes or photodiodes) of the detector. Measurements acquired using the detector may be used to determine offset, amplitude, and phase of a phase-contrast interference pattern without multiple acquisitions at different phase steps.