公开(公告)号：US12057444B2

公开(公告)日：2024-08-06

申请号：US17808364

申请日：2022-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Souvick Mitra ,  Alain F. Loiseau ,  Robert J. Gauthier, Jr. ,  Meng Miao ,  Anindya Nath ,  Wei Liang

IPC: H01L27/02 ,  H01L29/74

CPC classification number: H01L27/0262 ,  H01L29/7436

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.

公开(公告)号：US20240234305A1

公开(公告)日：2024-07-11

申请号：US18150831

申请日：2023-01-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh M. Pandey ,  Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Chung F. Tan ,  Judson R. Holt

IPC: H01L23/525 ,  H01L23/34 ,  H01L23/62

CPC classification number: H01L23/5256 ,  H01L23/345 ,  H01L23/62

Abstract: A structure includes: an electrically programmable fuse (e-fuse) including an anode and a cathode; at least one transistor positioned adjacent the e-fuse; and an electrically conductive interconnect coupling the cathode of the e-fuse to the at least one transistor, wherein the at least one transistor includes at least one semiconductor fin extending perpendicularly to the e-fuse.

公开(公告)号：US20240063212A1

公开(公告)日：2024-02-22

申请号：US17890725

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain F. Loiseau ,  Souvick Mitra ,  Rajendran Krishnasamy

IPC: H01L27/02 ,  H01L29/73 ,  H01L29/735 ,  H01L29/739

CPC classification number: H01L27/0255 ,  H01L29/7302 ,  H01L29/735 ,  H01L29/7393 ,  H01L27/0259

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure with a diode over a lateral bipolar transistor. A structure according to the disclosure may include a lateral bipolar transistor within a monocrystalline semiconductor over a substrate. An insulator layer is over a portion of the monocrystalline semiconductor. A diode is within a polycrystalline semiconductor on the insulator layer. A cathode of the diode is coupled to a first well within the monocrystalline semiconductor. The first well defines one of an emitter terminal and a collector terminal of the lateral bipolar transistor.

公开(公告)号：US20220115864A1

公开(公告)日：2022-04-14

申请号：US17068967

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya Nath ,  Zhiqing Li ,  Souvick Mitra ,  Alain Loiseau ,  Wei Liang

IPC: H02H9/04 ,  H01L27/02

Abstract: Embodiments of the disclosure provide an electrostatic discharge (ESD) device, including: an input pad; an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance.

公开(公告)号：US11088075B2

公开(公告)日：2021-08-10

申请号：US16671414

申请日：2019-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Souvick Mitra ,  Rainer Thoma ,  Harsh Shah ,  Anindya Nath ,  Robert J. Gauthier, Jr.

IPC: H01L23/528 ,  H01L21/74 ,  H01L29/417 ,  H01L23/522

Abstract: Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout.

公开(公告)号：US20210134719A1

公开(公告)日：2021-05-06

申请号：US16671414

申请日：2019-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Souvick Mitra ,  Rainer Thoma ,  Harsh Shah ,  Anindya Nath ,  Robert J. Gauthier, JR.

IPC: H01L23/528 ,  H01L23/522 ,  H01L29/417 ,  H01L21/74

Abstract: Back-end-of-line layout structures and methods of forming a back-end-of-line layout structure. A metallization level includes a plurality of interconnects positioned over a plurality of active device regions. The plurality of interconnects have a triangular-shaped layout and a plurality of lengths within the triangular-shaped layout.

公开(公告)号：US20250126817A1

公开(公告)日：2025-04-17

申请号：US18380917

申请日：2023-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Meng Miao ,  Alain Loiseau ,  Lin Lin ,  Jing Wan ,  Wei Liang ,  Anindya Nath ,  Sagar Premnath Karalkar ,  Souvick Mitra ,  Xunyu Li ,  Mengfu Di

IPC: H01L29/747 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers and methods of manufacture. The structure includes: a plurality of wells of a first conductivity type; a well of a second conductivity type which is different than the first conductivity type; an intrinsic semiconductor region between the well and the plurality of wells; and contacts within the plurality of wells.

公开(公告)号：US20250015074A1

公开(公告)日：2025-01-09

申请号：US18886381

申请日：2024-09-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya Nath ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/74

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertically stacked diode-trigger silicon controlled rectifiers and methods of manufacture. The structure includes: a silicon controlled rectifier in a trap rich region of a semiconductor substrate; and at least one diode built in polysilicon (gate material) and isolated by a gate-dielectric.

公开(公告)号：US11955472B2

公开(公告)日：2024-04-09

申请号：US17554222

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Meng Miao ,  Alain Loiseau ,  Souvick Mitra ,  Wei Liang ,  Robert J. Gauthier, Jr. ,  Anindya Nath

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L27/1207 ,  H01L29/7436

Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P− closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

公开(公告)号：US20240074167A1

公开(公告)日：2024-02-29

申请号：US17895156

申请日：2022-08-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Alain F. Loiseau

IPC: H01L27/112 ,  H01L23/525 ,  H01L29/735

CPC classification number: H01L27/11206 ,  H01L23/5256 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a circuit structure including an electrically programmable fuse (efuse) and lateral bipolar transistor. A structure of the disclosure includes a lateral bipolar transistor within a semiconductor layer and over a substrate. An insulator layer is over a portion of the semiconductor layer. An efuse structure is within a polycrystalline semiconductor layer and over the insulator layer. The efuse structure is over a current path through the lateral bipolar transistor.