公开(公告)号：US20250159999A1

公开(公告)日：2025-05-15

申请号：US18388441

申请日：2023-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Uppili S. Raghunathan ,  Rajendran Krishnasamy ,  Sagar Premnath Karalkar ,  Alexander M. Derrickson ,  Vibhor Jain

IPC: H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a silicon control rectifier (SCR) and methods of manufacture. The structure includes: a doped region in a semiconductor substrate; at least two regions of semiconductor material comprising opposite doping types over the doped region; and polysilicon regions over respective ones of the least two regions of semiconductor material.

公开(公告)号：US20250031457A1

公开(公告)日：2025-01-23

申请号：US18223780

申请日：2023-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  . Ajay ,  Souvick Mitra ,  Kyong Jin Hwang

IPC: H01L27/02

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a semiconductor substrate including a well, a field-effect transistor including a gate, a source having a doped region in the well, and a drain, and a silicon-controlled rectifier including a doped region in the well.

公开(公告)号：US20250126817A1

公开(公告)日：2025-04-17

申请号：US18380917

申请日：2023-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Meng Miao ,  Alain Loiseau ,  Lin Lin ,  Jing Wan ,  Wei Liang ,  Anindya Nath ,  Sagar Premnath Karalkar ,  Souvick Mitra ,  Xunyu Li ,  Mengfu Di

IPC: H01L29/747 ,  H01L27/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers and methods of manufacture. The structure includes: a plurality of wells of a first conductivity type; a well of a second conductivity type which is different than the first conductivity type; an intrinsic semiconductor region between the well and the plurality of wells; and contacts within the plurality of wells.

公开(公告)号：US12051690B2

公开(公告)日：2024-07-30

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.

公开(公告)号：US20240234409A1

公开(公告)日：2024-07-11

申请号：US18152420

申请日：2023-01-10

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem G. Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: The disclosure provides a structure including an n-type well over an n-type deep well and between a pair of p-type wells for electrostatic discharge (ESD) protection. The structure may include a p-type deep well over a substrate, a first n-type well over the p-type deep well, and a pair of p-type wells over the p-type deep well. The pair of p-type wells are each adjacent opposite horizontal ends of the n-type well. A pair of second n-type wells are over the p-type deep well and adjacent one of the pair of p-type wells. Each p-type well is horizontally between the first n-type well and one of the second n-type wells.

公开(公告)号：US20240170531A1

公开(公告)日：2024-05-23

申请号：US18056289

申请日：2022-11-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Jie Zeng ,  Souvick Mitra

IPC: H01L29/06 ,  H01L27/02

CPC classification number: H01L29/0623 ,  H01L27/0248

Abstract: The disclosure provides a structure with a buried doped region, and methods to form the same. A structure may include a semiconductor substrate including a first well. A first terminal includes a first doped region in the first well. A second terminal includes a second doped region in the first well. The first well horizontally separates the first doped region from the second doped region. A first buried doped region is in the first well. The first buried doped region overlaps with, and is underneath, the first doped region. The first well vertically separates the first doped region from the first buried doped region.

公开(公告)号：US20240429227A1

公开(公告)日：2024-12-26

申请号：US18213442

申请日：2023-06-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Vishal Ganesan ,  Kyong Jin Hwang ,  Souvick Mitra

IPC: H01L27/02

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises adjacent first and second gates over a semiconductor substrate, a source adjacent to the first gate, and a drain adjacent to the second gate. The source includes a first well in the semiconductor substrate, a second well in the semiconductor substrate, and a doped region. The first well and the doped region have a first conductivity type, and the second well has a second conductivity type opposite from the first conductivity type. The doped region has a first portion that overlaps with the first well, and the doped region has a second portion that overlaps with the second well.

公开(公告)号：US20240213240A1

公开(公告)日：2024-06-27

申请号：US18086938

申请日：2022-12-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Ephrem Gebreselasie ,  Rajendran Krishnasamy ,  Robert J. Gauthier, JR. ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262 ,  H01L21/76224

Abstract: Structures for an electrostatic discharge protection device and methods of forming same. The structure comprises a first well and a second well in the semiconductor substrate. The first and second wells have a first conductivity type. The structure further comprises a third well and a fourth well in the semiconductor substrate. The third and fourth wells have a second conductivity type, the third well includes a portion that overlaps with the first well, and the fourth well includes a portion that overlaps with the second well.

公开(公告)号：US11776952B1

公开(公告)日：2023-10-03

申请号：US17737272

申请日：2022-05-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Jie Zeng ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/66

CPC classification number: H01L27/0262 ,  H01L29/66363 ,  H01L29/74

Abstract: Structures for a silicon-controlled rectifier and methods of forming a structure for a silicon-controlled rectifier. The structure includes first and second wells in the semiconductor substrate, a first terminal including a first doped region in the first well, and a second terminal including a second doped region in the second well. The first well and the second doped region have a first conductivity type, and the second well and the first doped region have a second conductivity type opposite to the first conductivity type. First and second conductor layers are positioned on the semiconductor substrate. The first conductor layer partially overlaps with the first well, and the second conductor layer partially overlaps with the second well. A third doped region, which has the second conductivity type, is laterally positioned in the semiconductor substrate between the first and second conductor layers.

公开(公告)号：US20230141491A1

公开(公告)日：2023-05-11

申请号：US17523956

申请日：2021-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sagar Premnath Karalkar ,  Prantik Mahajan ,  Jie Zeng ,  Ajay Ajay ,  Milova Paul ,  Souvick Mitra

IPC: H01L27/02

CPC classification number: H01L27/0262

Abstract: Disclosed is a semiconductor structure including a semiconductor substrate (e.g., a P-substrate) and a symmetric BDSCR. The BDSCR includes, within the substrate, a first well (e.g., a low-doped deep Nwell) and, within the first well, symmetric side sections and a middle section positioned laterally between the side sections. Each side section includes: second and third wells (e.g., Pwells), where the third well is shallower than and has a higher conductivity level than the second well. Each middle section includes multiple floating wells including: two fourth wells (e.g., Nwells), which have a higher conductivity level than the first well, and a fifth well (e.g., another Pwell), which is positioned laterally between and shallower than the fourth wells. By incorporating the floating wells into the middle section, high current tolerance is improved.