公开(公告)号：US11437522B2

公开(公告)日：2022-09-06

申请号：US16890063

申请日：2020-06-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Mark Levy ,  Rajendran Krishnasamy ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/786 ,  H01L21/763 ,  H01L29/06 ,  H01L29/423

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A shallow trench isolation region is formed in a semiconductor substrate. A trench is formed in the shallow trench isolation region, and a body region is formed in the trench of the shallow trench isolation region. The body region is comprised of a polycrystalline semiconductor material.

公开(公告)号：US20220190145A1

公开(公告)日：2022-06-16

申请号：US17120916

申请日：2020-12-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sarah McTaggart ,  Qizhi Liu ,  Vibhor Jain ,  Mark Levy ,  Paula Fisher ,  James R. Elliott

IPC: H01L29/737 ,  H01L29/66

Abstract: Device structures and fabrication methods for heterojunction bipolar transistors. Trench isolation regions are positioned in a semiconductor substrate to define active regions. A base layer includes first sections that are respectively positioned over the active regions and second sections that are respectively positioned over the trench isolation regions. Emitter fingers are respectively positioned on the first sections of the base layer. The first sections of the base layer include single-crystal semiconductor material, and the second sections of the base layer include polycrystalline semiconductor material. The second sections of the base layer are spaced in a vertical direction from the trench isolation regions to define a first cavity that extends about a perimeter of the base layer and second cavities that are connected to the first cavity.

公开(公告)号：US12002878B2

公开(公告)日：2024-06-04

申请号：US18085677

申请日：2022-12-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark Levy ,  Jeonghyun Hwang

IPC: H01L29/778 ,  H01L27/088 ,  H01L29/04 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/7783 ,  H01L27/088 ,  H01L29/04 ,  H01L29/1602 ,  H01L29/2003 ,  H01L29/66462

Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

公开(公告)号：US20240014101A1

公开(公告)日：2024-01-11

申请号：US17858660

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Cameron Luce ,  Siva P. Adusumilli ,  Mark Levy

IPC: H01L23/473 ,  H01L23/367 ,  H01L21/762 ,  H01L29/51

CPC classification number: H01L23/473 ,  H01L23/367 ,  H01L21/76229 ,  H01L29/515

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a trench in a semiconductor substrate and a semiconductor layer inside the trench. The trench has an entrance and a sidewall extending from the entrance into the semiconductor substrate. The semiconductor layer has a first portion surrounding a portion of the trench to define a cavity and a second portion positioned to obstruct the entrance to the trench. The second portion of the semiconductor layer is thicker than the first portion of the semiconductor layer.

公开(公告)号：US20240009668A1

公开(公告)日：2024-01-11

申请号：US17858461

申请日：2022-07-06

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ramsey Hazbun ,  Siva P. Adusumilli ,  Mark Levy ,  Bartlomiej Jan Pawlak

IPC: B01L3/00 ,  B81B1/00 ,  B81C1/00

CPC classification number: B01L3/50273 ,  B81B1/002 ,  B81C1/00071 ,  B81B2201/05 ,  B81B2203/0338 ,  B01L2300/0645 ,  B01L2300/12 ,  B01L2400/0424

Abstract: Structures for a microfluidic channel and methods of forming a structure for a microfluidic channel. The structure comprises a semiconductor substrate including a trench and a layer stack on the semiconductor substrate. The layer stack includes a first layer, a second layer between the first layer and the semiconductor substrate, and an opening penetrating through the first layer and the second layer to the trench. The structure further comprises a third layer inside the opening in the layer stack. The third layer, which comprises a semiconductor material, obstructs the opening to define a cavity inside the trench.

公开(公告)号：US11768337B2

公开(公告)日：2023-09-26

申请号：US17362154

申请日：2021-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Spencer Porter ,  Mark Levy ,  Siva P. Adusumilli ,  Yusheng Bian

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/12

CPC classification number: G02B6/4203 ,  G02B6/1225 ,  G02B2006/12104 ,  G02B2006/12159

Abstract: Structures for a coupler and methods of forming a structure for a coupler. A structure for a directional coupler may include a first waveguide core having one or more first airgaps and a second waveguide core including one or more second airgaps. The one or more second airgaps are positioned in the second waveguide core adjacent to the one or more first airgaps in the first waveguide core. A structure for an edge coupler is also provided in which the waveguide core of the edge coupler includes one or more airgaps.

公开(公告)号：US20230125886A1

公开(公告)日：2023-04-27

申请号：US17506992

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N.R. Vanukuru ,  Mark Levy

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

公开(公告)号：US20230121393A1

公开(公告)日：2023-04-20

申请号：US18085677

申请日：2022-12-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark Levy ,  Jeonghyun Hwang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/16 ,  H01L29/04 ,  H01L27/088 ,  H01L29/66

Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

公开(公告)号：US20220392888A1

公开(公告)日：2022-12-08

申请号：US17890446

申请日：2022-08-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Mark Levy ,  Jeonghyun Hwang ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8258 ,  H01L29/06 ,  H01L29/04

Abstract: Structures including devices, such as transistors, integrated on a bulk semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a bulk semiconductor substrate. The bulk semiconductor substrate contains a single-crystal semiconductor material having a diamond crystal lattice structure and a crystal orientation. A first transistor is formed in a first device region of the bulk semiconductor substrate, and a second transistor is formed in a second device region of the bulk semiconductor substrate. The second transistor includes a layer stack on the bulk semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material.

公开(公告)号：US11195715B2

公开(公告)日：2021-12-07

申请号：US16821228

申请日：2020-03-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Cameron Luce ,  Ramsey Hazbun ,  Mark Levy ,  Anthony K. Stamper ,  Alvin J. Joseph

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/324

Abstract: Methods of forming structures with electrical isolation. A dielectric layer is formed over a semiconductor substrate, openings are patterned in the dielectric layer that extend to the semiconductor substrate, and a semiconductor material is epitaxially grown from portions of the semiconductor substrate that are respectively exposed inside the openings. The semiconductor material, during growth, defines a semiconductor layer that includes first portions respectively coincident with the openings and second portions that laterally grow from the first portions to merge over a top surface of the dielectric layer. A modified layer containing a trap-rich semiconductor material is formed in the semiconductor substrate.