公开(公告)号：US20230063731A1

公开(公告)日：2023-03-02

申请号：US17983436

申请日：2022-11-09

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US11581450B2

公开(公告)日：2023-02-14

申请号：US16899028

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Vibhor Jain ,  John J. Ellis-Monaghan

IPC: H01L31/101 ,  H01L31/107 ,  H01L31/18 ,  H01L31/0352

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one vertical pillar feature within a trench; a photosensitive semiconductor material extending laterally from sidewalls of the at least one vertical pillar feature; and a contact electrically connecting to the photosensitive semiconductor material.

公开(公告)号：US11569374B2

公开(公告)日：2023-01-31

申请号：US17109538

申请日：2020-12-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Mark Levy ,  Jeonghyun Hwang

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/16 ,  H01L29/04 ,  H01L27/088 ,  H01L29/66

Abstract: Structures including devices, such as transistors, integrated on a semiconductor substrate and methods of forming a structure including devices, such as transistors, integrated on a semiconductor substrate. A first transistor is formed in a first device region of a semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer comprised of a III-V compound semiconductor material. A polycrystalline layer includes a section that is positioned in the semiconductor substrate beneath the first device region.

公开(公告)号：US11515158B2

公开(公告)日：2022-11-29

申请号：US16815070

申请日：2020-03-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramsey Hazbun ,  Alvin J. Joseph ,  Siva P. Adusumilli ,  Cameron Luce

IPC: H01L21/02

Abstract: Disclosed are semiconductor structure embodiments of a semiconductor-on-insulator region on a bulk substrate. The semiconductor-on-insulator region includes an upper semiconductor layer above and physically separated from the substrate by insulator-containing cavities (e.g., by dielectric layer and/or a pocket of trapped air, of trapped gas, or under vacuum) and, optionally, by a lower semiconductor layer. Disclosed method embodiments include forming openings that extend vertically through the upper semiconductor layer, through a sacrificial semiconductor layer and, optionally, through a lower semiconductor layer to the substrate. Then, a selective isotropic etch process is performed to form cavities, which extend laterally off the sides of the openings into the sacrificial semiconductor layer. Depending upon the embodiments, different process steps are further performed to form plugs in at least the upper portions of the openings and insulators (including dielectric layers and/or a pocket of trapped air, of trapped gas or under vacuum) in the cavities.

公开(公告)号：US11444149B1

公开(公告)日：2022-09-13

申请号：US17182415

申请日：2021-02-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Yves T. Ngu ,  Mickey H. Yu

IPC: H01L27/12 ,  H01L27/06 ,  H01L49/02 ,  H01L27/08

Abstract: A resistor includes at least one polysilicon resistor element in a semiconductor substrate with each polysilicon resistor element having a continuous U-shape with a continuous lateral bottom. The resistor may include an insulator within a valley of the U-shape of each polysilicon resistor element. A plurality of polysilicon resistor elements can be sequentially interconnected to create a serpentine polysilicon resistor. The resistor may also include a dopant-including high resistivity (HR) polysilicon layer thereunder to provide electrical isolation from, and better thermal conduction to, for example, a base semiconductor substrate. The resistor can be used in an SOI substrate. A related method is also disclosed.

公开(公告)号：US11437329B2

公开(公告)日：2022-09-06

申请号：US17070377

申请日：2020-10-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Johnatan A. Kantarovsky ,  Vibhor Jain ,  Siva P. Adusumilli ,  Ajay Raman ,  Sebastian T. Ventrone ,  Yves T. Ngu

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/522 ,  H01L49/02

Abstract: The present disclosure relates to integrated circuits, and more particularly, to an anti-tamper x-ray blocking package for secure integrated circuits and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: one or more devices on a front side of a semiconductor material; a plurality of patterned metal layers under the one or more devices, located and structured to protect the one or more devices from an active intrusion; an insulator layer between the plurality of patterned metal layers; and at least one contact providing an electrical connection through the semiconductor material to a front side of the plurality of metals.

公开(公告)号：US20220189818A1

公开(公告)日：2022-06-16

申请号：US17118697

申请日：2020-12-11

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Fuad H. Al-Amoody ,  Felix P. Anderson ,  Spencer H. Porter ,  Mark D. Levy ,  Siva P. Adusumilli

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/417

Abstract: Disclosed is a structure with ultralow-K (ULK) dielectric-gap wrapped contact(s). The structure includes an opening, which extends through a dielectric layer and is aligned above a device. A contact is within the opening and electrically connected to the device. Instead of the contact completely filling the opening, a ULK dielectric-gap (e.g., an air or gas-filled gap or a void) at least partially separates the contact from the sidewall(s) of the contact opening and further wraps laterally around the contact. Also disclosed is a method for forming the structure and, particularly, for forming a ULK dielectric-gap by etching back an exposed top end of an adhesive layer initially lining a contact opening to form a gap between the sidewall(s) of the opening and the contact and then capping the gap with an additional dielectric layer such that the gap is filled with air or gas or is under vacuum.

公开(公告)号：US11316019B2

公开(公告)日：2022-04-26

申请号：US16942734

申请日：2020-07-29

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Johnatan Avraham Kantarovsky ,  Rajendran Krishnasamy ,  Siva P. Adusumilli ,  Steven Bentley ,  Michael Joseph Zierak ,  Jeonghyun Hwang

IPC: H01L29/40 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to semiconductor devices having field plates that are arranged symmetrically around a gate. The present disclosure provides a semiconductor device including an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region and laterally between the source and drain electrodes, a first field plate between the source electrode and the gate, a second field plate between the drain electrode and the gate, in which the gate is spaced apart laterally and substantially equidistant from the first field plate and the second field plate.

公开(公告)号：US11164867B2

公开(公告)日：2021-11-02

申请号：US16534361

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Julien Frougier ,  Ruilong Xie ,  Anthony K. Stamper

IPC: H01L29/04 ,  H01L29/786 ,  H01L27/088 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/324

Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

公开(公告)号：US11056382B2

公开(公告)日：2021-07-06

申请号：US15924444

申请日：2018-03-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Siva P. Adusumilli ,  Steven M. Shank

IPC: H01L29/78 ,  H01L21/762 ,  H01L23/48 ,  H01L21/768

Abstract: Structures with a cavity beneath semiconductor devices and methods associated with forming such substrates. A first semiconductor layer is formed on a first side of a first handle wafer. A device structure is formed that is arranged at least in part in the first semiconductor layer. After forming the device structure, the first handle wafer is thinned from a second side of the first handle wafer opposite to the first side of the first handle wafer in order to form a second semiconductor layer from the first handle wafer. After thinning the first handle wafer, a cavity is formed in the second semiconductor layer. The cavity is arranged in the second semiconductor layer beneath the device structure. A second handle wafer is attached to the second semiconductor layer to close the cavity.