公开(公告)号：GB2552266B

公开(公告)日：2018-05-23

申请号：GB201711974

申请日：2016-03-09

Applicant: IBM

Inventor： WALTER HAEBERLE ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA

IPC: G01V3/08 ,  G01R33/09

公开(公告)号：GB2515568B

公开(公告)日：2016-05-18

申请号：GB201311671

申请日：2013-06-28

Applicant: IBM

Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  DANIEL KREBS ,  ABU SEBASTIAN

IPC: G11C13/00 ,  G11C13/02 ,  H01L45/00

公开(公告)号：GB2581731B

公开(公告)日：2022-11-09

申请号：GB202006982

申请日：2018-10-23

Applicant: IBM

Inventor： MANUEL LE GALLO-BOURDEAU ,  ABU SEBASTIAN ,  IREM BOYBAT KARA ,  EVANGELOS STAVROS ELEFTHERIOU ,  NANDAKUMAR SASIDHARAN RAJALEKSHMI

IPC: G06N3/08 ,  G06N3/063

Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of layers of neurons interposed with layers of synapses. A set of crossbar arrays of memristive devices, connected between row and column lines, implements the layers of synapses. Each memristive device stores a weight for a synapse interconnecting a respective pair of neurons in successive neuron layers. The training method includes performing forward propagation, backpropagation and weight-update operations of an iterative training scheme by applying input signals, associated with respective neurons, to row or column lines of the set of arrays to obtain output signals on the other of the row or column lines, and storing digital signal values corresponding to the input and output signals. The weight-update operation is performed by calculating digital weight-correction values for respective memristive devices, and applying programming signals to those devices to update the stored weights.

公开(公告)号：GB2581731A

公开(公告)日：2020-08-26

申请号：GB202006982

申请日：2018-10-23

Applicant: IBM

Inventor： MANUEL LE GALLO-BOURDEAU ,  ABU SEBASTIAN ,  IREM BOYBAT KARA ,  EVANGELOS STAVROS ELEFTHERIOU ,  NANDAKUMAR SASIDHARAN RAJALEKSHMI

IPC: G06N3/08 ,  G06N3/063

Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of layers of neurons interposed with layers of synapses. A set of crossbar arrays of memristive devices, connected between row and column lines, implements the layers of synapses. Each memristive device stores a weight Ŵ for a synapse interconnecting a respective pair of neurons in successive neuron layers. The training method comprises performing forward propagation, backpropagation and weight-update operations of an iterative training scheme by, in at least one of the forward propagation and backpropagation operations of the scheme, applying input signals, associated with respective neurons, to one of row and column lines of the set of arrays to obtain output signals on the other of the row and column lines, and storing digital signal values corresponding to the input and output signals in a digital processing unit operatively coupled to the set of arrays. The weight-update operation of the scheme is performed by calculating, in the digital processing unit, digital weight-correction values ΔW, dependent on the stored digital signal values, for respective memristive devices, and applying programming signals to those devices to update the stored weights Ŵ in dependence on the respective digital weight-correction values ΔW.

公开(公告)号：GB2580837A

公开(公告)日：2020-07-29

申请号：GB202005840

申请日：2018-09-13

Applicant: IBM ,  RWTH AACHEN

Inventor： WABE KOELMANS ,  ABU SEBASTIAN ,  VARA JONNALAGADDA ,  MARTIN SALINGA ,  BENEDIKT KERSTING

IPC: G11C11/56 ,  H10B99/00

Abstract: The invention is notably directed to a resistive memory device comprising a control unit for controlling the resistive memory device and a plurality of memory cells. The plurality of memory cells includes a first terminal, a second terminal and a phase change segment comprising a phase-change material for storing information in a plurality of resistance states. The phase change segment is arranged between the first terminal and the second terminal. The phase change material consists of antimony. Furthermore, at least one of the dimensions of the phase change segment is smaller than 15 nanometers. Additional implementations of the resistive memory device include a related method, a related control unit, a related memory cell and a related computer program product.

公开(公告)号：GB2556550A

公开(公告)日：2018-05-30

申请号：GB201801088

申请日：2016-06-08

Applicant: IBM

Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  MANUEL LE GALLO ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA

IPC: G06N3/04 ,  G06N3/063

Abstract: A neuromorphic processing device (1) has a device input (2), for receiving an input data signal, and an assemblage of neuron circuits (3). Each neuron circuit (3) comprises a resistive memory cell (14) which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals (11) for programming cell resistance to vary the neuron state, and a neuron output circuit (15) for supplying a neuron output signals (12) in response to cell resistance traversing a threshold. The device (1) includes an input signal generator (4) connected to the device input (2) and the assemblage of neuron circuits (3), for generating neuron input signals (11) for the assemblage in dependence on the input data signal. The device (1) further includes a device output circuit (5), connected to neuron output circuits (15) of the assemblage, for producing a device output signal dependent on neuron output signals (12) of the assemblage, whereby the processing device (1) exploits stochasticity of resistive memory cells of the assemblage.

公开(公告)号：GB2552577B

公开(公告)日：2018-05-02

申请号：GB201708045

申请日：2015-10-13

Applicant: IBM

Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA

IPC: G06N3/063

Abstract: A neuromorphic synapse with a resistive memory cell connected in circuitry having first and second input terminals. The input terminals respectively receive pre-neuron and post-neuron action signals, each having a read portion and a write portion, in use. The circuitry includes an output terminal for providing a synaptic output signal which is dependent on resistance of the memory cell. The circuitry is configured such that the synaptic output signal is provided at the output terminal in response to application at the first input terminal of the read portion of the pre-neuron action signal, and such that a programming signal, for programming resistance of the memory cell, is applied to the cell in response to simultaneous application of the write portions of the pre-neuron and post-neuron action signals at the first and second input terminals respectively. The synapse can be adapted for operation with identical pre-neuron and post-neuron action signals.

公开(公告)号：GB2532787A

公开(公告)日：2016-06-01

申请号：GB201421183

申请日：2014-11-28

Applicant: IBM

Inventor： ANGELIKI PANTAZI ,  TOMAS TUMA ,  ABU SEBASTIAN

IPC: G01D5/12 ,  G01B7/00 ,  G01R33/09

Abstract: A sensor arrangement for position sensing comprises a magnetic field source (2) and a magnetoresistive element (1) arranged in a magnetic field generated by the magnetic field source (2). The magnetoresistive element (1) provides an output signal (R) dependent on a position (x) of the magnetoresistive element (1) relative to the magnetic field source (2). A feedback controller (3) is configured to receive the output signal (R) of the magnetoresistive element (1) and is configured to adjust one or more of the position (x) of the magnetoresistive element relative to the magnetic field source (2) and a the strength of the magnetic field generated by the magnetic field source (2) acting on the magnetoresistive element dependent on the output signal (R) of the magnetoresistive element. The sensor comprises a conductive layer between two magnetic layers.