公开(公告)号：US3582906A

公开(公告)日：1971-06-01

申请号：US3582906D

申请日：1969-06-27

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  BROWN PAUL J

IPC: G06F13/10 ,  G06F13/42 ,  G06F15/16

CPC classification number: G06F13/4269

Abstract: A communication system which connects input/output (I/O) devices of different data rates with a data processing system. Transfer of the first byte of data to the data processing system from an I/O device is synchronized with the rise of an inbound tag from the I/O device. Receipt of the first byte by the data processing system is signalled by raising the outbound tag, following which the device drops the inbound tag. Transfer of the second byte from the I/O device is synchronized with the rise of a data in tag. Receipt of the second byte is signalled by raising the data out tag. The outbound tag is dropped after the inbound tag has dropped. The data out tag is dropped after the data in tag has dropped. Transfer of data to the device from the data processing system utilizes the same sequence, however, transfer of the first byte is synchronized with the rise of the outbound tag and transfer of the second byte is synchronized with the rise of data out.

公开(公告)号：US3189872A

公开(公告)日：1965-06-15

申请号：US18102762

申请日：1962-03-20

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  GALAGE DOMINICK J

IPC: G06F11/08 ,  G06F11/10

CPC classification number: G06F11/10 ,  G06F11/08

公开(公告)号：US3897626A

公开(公告)日：1975-08-05

申请号：US33418173

申请日：1973-02-20

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

IPC: G06F11/10 ,  G11C29/00 ,  H01L21/70 ,  B01J17/00 ,  H01L21/98

CPC classification number: G11C29/76 ,  G06F11/1024 ,  G11C29/88

Abstract: A computer memory, most particularly a monolithic memory, may be constructed of components which contain defective bit cells. During the production process, the monolithic chips are sorted into groups in accordance with the chip sector which contains one or more defective cells. The chips are then mounted on memory cards, with all of the chips which have a defect in a given chip sector being mounted on a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The address wiring of the memory is provided in such a manner as to ensure that no given memory word, or defined group of bits within a memory word, contains within it more than one memory cell that is known or suspected to be defective. Means are also provided for deriving from the address of any given memory word the bit location within said word of a defective or suspicious bit. In one embodiment shown herein, the suspect bit is bypassed in favor of a redundant bit provided within the memory system. In another embodiment described herein, the suspect bit is utilized just as if it were a good bit, but, upon detection of an error, the suspect bit will be presumed to be in error.

Abstract translation: 计算机存储器，特别是单片存储器，可以由包含有缺陷位单元的组件构成。 在生产过程中，根据包含一个或多个缺陷单元的芯片扇区将单片芯片分组成一组。 然后将这些芯片安装在存储卡上，所有在给定芯片区域中具有缺陷的芯片被安装在相应的卡片扇区上。 然后，以基本相同的方式产生每个卡的卡被组装成完整的存储器。 提供存储器的地址布线以确保没有给定的存储器字或存储器字中的定义的位组在其内包含多于一个已知或怀疑是有缺陷的存储器单元。 还提供了用于从任何给定存储器字的地址导出有缺陷或可疑位的所述字内的位位置的装置。 在本文所示的一个实施例中，可疑位被旁路以有利于提供在存储器系统内的冗余位。 在本文描述的另一实施例中，可疑位被利用，好像它是一个好位，但是在检测到错误时，怀疑位将被认为是错误的。

公开(公告)号：US3704452A

公开(公告)日：1972-11-28

申请号：US3704452D

申请日：1970-12-31

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  BROWN DAVID T ,  CLARK WILLIAM A

IPC: G06F3/00 ,  G06F7/78 ,  G11C19/28 ,  G06F9/20 ,  H03K5/00

CPC classification number: G06F7/78 ,  G06F3/007 ,  G11C19/287

Abstract: A data storage unit is provided in which groups or ''''pages'''' of data including their addresses are stored in shift registers in successive positions, the registers being operable on a signal requesting access to shift their contents repetitively to the next position in one or more loops which include a position wherein a page may be accessed and in one or more loops which excludes said access position. Controls are provided for varying the shifting in said loops such that the positions of some or all of the pages of separately accessed classes are dynamically reordered so that they are presented to said access position on such signal in approximately or exactly the order in which they were last requested, thus reducing average access time in programs involving considerable repeated reference to a limited group of pages of the class.

Abstract translation: 提供了一种数据存储单元，其中包括其地址的数据的组或“页”在连续位置中被存储在移位寄存器中，该寄存器可以在请求访问的信号上操作以将它们的内容重复地移动到一个或多个循环中的下一个位置 其包括可以访问页面的位置以及排除所述访问位置的一个或多个循环。 提供控制以改变所述环路中的移位，使得单独访问的类别的一些或全部页面的位置被动态地重新排序，使得它们以大致或恰好其大致或顺序的顺序被呈现给该信号上的所述访问位置 最后请求，从而减少程序中的平均访问时间，重复参考有限的一组页面。

公开(公告)号：US3648254A

公开(公告)日：1972-03-07

申请号：US3648254D

申请日：1969-12-31

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

IPC: G11C15/04 ,  G06F17/30 ,  G06F7/34

CPC classification number: G06F17/30982

Abstract: An associative search apparatus for an electronic bulk storage in which data are stored in parallel by word in a plurality of memory elements in which data bits are electronically rotatable. The memory elements are selectable by a memory selection matrix. Search tables are organized on a modular basis so that the simultaneous search of many table entries is accomplished at one time. Smaller or larger logical entries are searched within the system by executing several search operations. The first search operation marks the location of where word match conditions occurred in the first table search. The second search operation compares the second search argument against the second table only at the same relative positions where matches occurred in the first table. Marking enables any table regardless of size to be searched by using the results of a previous search operation to determine the entries to be searched on subsequent search operations.

Abstract translation: 一种用于电子大容量存储器的关联搜索装置，其中数据在数据位可电子旋转的多个存储元件中以字并行存储。 存储器元件可由存储器选择矩阵选择。 搜索表以模块化的方式组织，以便同时搜索许多表条目。 通过执行多个搜索操作，在系统内搜索较小或更大的逻辑条目。 第一搜索操作标记在第一表搜索中发生字匹配条件的位置。 第二搜索操作仅在与第一表中发生匹配的相同相对位置处比较第二搜索参数与第二表。 通过使用先前搜索操作的结果来确定在随后的搜索操作中要搜索的条目，可以进行任何表格的搜索，无论使用何种大小进行搜索。

公开(公告)号：US3644902A

公开(公告)日：1972-02-22

申请号：US3644902D

申请日：1970-05-18

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

IPC: G06F11/10 ,  G11C29/00 ,  G06F13/00

CPC classification number: G11C29/88 ,  G06F11/1044

Abstract: A memory having circuits for correcting single errors in a word read from the memory is provided with means to reconfigure the memory so that a configuration having a double, uncorrectable, error is changed to a configuration having two single, correctable errors. In one embodiment, interchanging plug-in components for two or more bit positions produces a new configuration; in another embodiment, the wiring to the plug-in components is easily changeable.

公开(公告)号：US3582880A

公开(公告)日：1971-06-01

申请号：US3582880D

申请日：1969-12-05

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  ROHDE RICHARD S ,  SMITH RONALD M ,  ZEIGER HENRY

IPC: G06F11/16 ,  G06F11/00 ,  G08C25/00

CPC classification number: G06F11/1612

Abstract: A system for sending and receiving data and detecting data errors for correction which includes means for detecting an error in data as it is read from a tape or like device and means for forwarding the data with the error into a further storage point in the system where it is stored for a first time. A second cycle or storage of the data with the error in the storage point is called for, the data with error being arranged to distinguish it from the arrangement of the error data as it existed at the first time at the storage point. The two versions of the same data having error therein are compared to detect and correct the data in error.

公开(公告)号：US3400372A

公开(公告)日：1968-09-03

申请号：US43297065

申请日：1965-02-16

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HOSKINSON WILLIAM C ,  KING LEWIS E ,  WEBER III HERBERT G

IPC: G06F13/10 ,  G06F13/12 ,  G06F15/16 ,  G06F15/17 ,  G06F15/177

CPC classification number: G06F15/17 ,  G06F13/122

公开(公告)号：US3336582A

公开(公告)日：1967-08-15

申请号：US39361164

申请日：1964-09-01

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  CALVERT JAMES D ,  ANDRIS PADEGS

IPC: G06F13/20 ,  G06F13/38 ,  G06F13/42 ,  H04L5/00

CPC classification number: H04L5/00 ,  G06F13/20 ,  G06F13/38 ,  G06F13/4213

公开(公告)号：CA960363A

公开(公告)日：1974-12-31

申请号：CA186211

申请日：1973-11-20

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  KEEFE GEORGE E ,  WALKER ERNEST L

IPC: G11C11/14 ,  G01R33/09 ,  G11C19/08

Abstract: A plurality of magneto-resistive sensing elements are connected in series and positioned adjacent magnetic bubble domain propagation paths in a compressor circuit. If a data representing bubble is injected into the beginning of the circuit, each bubble already present is forced over to the next idler position. As the bubbles pass the sensing elements their magnetization vectors are rotated producing corresponding changes in the resistance values of the sensors, which may be easily detected as a large magnitude signal indicating the presence of a data bubble.