中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

22 records (took 0.016 seconds)

    Interactive tie-breaking system
    1.
    发明授权
    Interactive tie-breaking system 失效
    互动式破碎系统

    公开(公告)号：US3676860A

    公开(公告)日：1972-07-11

    申请号：US3676860D

    申请日：1970-12-28

    Applicant: IBM

    Inventor： COLLIER WILLIAM W ,  SMITH RONALD M

    IPC: G06F9/46 ,  G06F13/18 ,  G06F9/18 ,  G05B19/22

    CPC classification number: G06F9/52 ,  G06F13/18

    Abstract: A multiple processor tie-breaking method separately and asynchronously used by each of any number of plural processors contending for a serially reusable resource (SRR). The contending processors independently and asynchronously interact in their use of the tie-breaking method to choose among themselves which processor will get the SRR. The method uses a common group of registers (or fields) accessible to all contending processors. The method permits uncoordinated fetching and storing of bits in those registers. Only one bit at a time need be fetched or changed by any processor. In fact, the plural independent processors can concurrently fetch or store the same bit in the common group of registers without affecting the reliability of the method. The priorities among processors dynamically change with every contention in a manner which gives each processor an equitable and equal chance of getting the SRR.

    Abstract translation: 分立和异步地使用多处理器断开方法，其中任意数量的多个处理器中的每个处理器争用可串行重复使用的资源（SRR）。 竞争的处理器在使用破产方法时独立和异步地进行交互，从而在其中选择哪个处理器将获得SRR。

    Vector processing.
    2.
    发明公开
    Vector processing. 失效
    向量处理。

    公开(公告)号：EP0205809A2

    公开(公告)日：1986-12-30

    申请号：EP86105482

    申请日：1986-04-21

    Applicant: IBM

    Inventor： BUCHHOLZ WERNER ,  SMITH RONALD M ,  WEHRLY DAVID S

    IPC: G06F9/48 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16 ,  G06F15/347

    CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30065 ,  G06F9/325 ,  G06F15/8084

    Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.

    Data error correction by inversion storage
    3.
    发明授权
    Data error correction by inversion storage 失效
    数据错误校正由反转存储

    公开(公告)号：US3582880A

    公开(公告)日：1971-06-01

    申请号：US3582880D

    申请日：1969-12-05

    Applicant: IBM

    Inventor： BEAUSOLEIL WILLIAM F ,  ROHDE RICHARD S ,  SMITH RONALD M ,  ZEIGER HENRY

    IPC: G06F11/16 ,  G06F11/00 ,  G08C25/00

    CPC classification number: G06F11/1612

    Abstract: A system for sending and receiving data and detecting data errors for correction which includes means for detecting an error in data as it is read from a tape or like device and means for forwarding the data with the error into a further storage point in the system where it is stored for a first time. A second cycle or storage of the data with the error in the storage point is called for, the data with error being arranged to distinguish it from the arrangement of the error data as it existed at the first time at the storage point. The two versions of the same data having error therein are compared to detect and correct the data in error.

    Shared data controlled by a plurality of users
    5.
    发明授权
    Shared data controlled by a plurality of users 失效
    由多个用户控制的共享数据

    公开(公告)号：US3886525A

    公开(公告)日：1975-05-27

    申请号：US37522473

    申请日：1973-06-29

    Applicant: IBM

    Inventor： BROWN PAUL J ,  SMITH RONALD M

    IPC: G06F12/14 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F15/16 ,  G06F15/177 ,  G06F9/12 ,  G06F9/18

    CPC classification number: G06F9/526 ,  G06F2209/521

    Abstract: A data processing technique is disclosed which permits a plurality of users of a data processing system to share data in a data store, providing independent and asynchronous access to the data for subsequent processing by either user. The sharing of small data items is accomplished without requiring the use of interlocks to prevent one user from obtaining access to the shared data item while the other is processing the data for subsequent replacement in the shared data store. In addition, sharing of data items of sufficient size permit the user to build up controls for safe and efficient sharing of data items of any size.

    VECTOR PROCESSING
    7.
    发明专利
    VECTOR PROCESSING 失效

    公开(公告)号：JPS61290570A

    公开(公告)日：1986-12-20

    申请号：JP11099086

    申请日：1986-05-16

    Applicant: IBM

    Inventor： BUCHHOLZ WERNER ,  SMITH RONALD M ,  WEHRLY DAVID S

    IPC: G06F9/48 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F17/16

    Abstract: A vector processor is disclosed which processes vectors that can have more elements than a vector register can contain at one time. Vectors are processed in sections in which the section size is determined by the number of element locations in a vector register. A vector count register controls the number of elements processed by each vector instruction. A vector interruption index points to the first or next element in a vector to be processed by a vector instruction either when it is first issued or when it is re-issued following an interruption of the vector instruction. A general purpose (length) register contains the entire length of the vector to be 1 processed. A single instruction, which starts a vector sectioning loop, provides for the smaller of the section size or the content of the length register to be loaded into the vector count register. During the operation of the sectioning loop, the vector count register is repetitively subtracted from the content of the first general purpose register and the resulting residual vector length is placed back in the first general purpose register until all of the elements have been processed.

    8.
    发明专利
    未知

    公开(公告)号：DE3483120D1

    公开(公告)日：1990-10-11

    申请号：DE3483120

    申请日：1984-06-20

    Applicant: IBM

    Inventor： GUM PETER H ,  SMITH RONALD M ,  LEVIN ARTHUR L ,  WILSON JOHN H

    IPC: G06F11/28 ,  G06F11/36 ,  G06F15/16 ,  G06F15/177 ,  G06F11/00

    Abstract: The method provides a separate trace table (TT) for each CPU in an MP (multiprocessor) to avoid inter-CPU interference in making trace table entries (16) for explicit and implicit tracing instructions enabled by flag bits (E, A, B) in a control register (CR). Explicit tracing entries are made for an enabled explicit tracing (TR) instruction (11). Implicit tracing entries are made for predetermined instructions (when enabled for tracing) which do not have tracing as their primary purpose. A storage operand (12) of the trace instruction (11) contains a disablement field (T) and optionally may contain an enablement-controlling class field (4...7) to improve the integrity of traceable programs. A time stamp and a range of general register (R1...R3) contents is provided in each trace table entry for a tracing instruction. The time stamp enables all trace tables in an MP system to be later merged into a single trace table whenever required.

Patent Agency Ranking