公开(公告)号：NZ233538A

公开(公告)日：1992-06-25

申请号：NZ23353890

申请日：1990-05-02

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08 ,  G06F13/16

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：DD295260A5

公开(公告)日：1991-10-24

申请号：DD34178390

申请日：1990-06-15

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F12/02

公开(公告)号：BR9002878A

公开(公告)日：1991-08-20

申请号：BR9002878

申请日：1990-06-18

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F13/36 ,  G06F12/00 ,  G06F12/02 ,  G06F13/28 ,  G06F13/42 ,  G06F13/00

Abstract: A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode.

公开(公告)号：BR9002555A

公开(公告)日：1991-08-13

申请号：BR9002555

申请日：1990-05-30

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08 ,  G06F15/20

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：AU5506690A

公开(公告)日：1990-12-06

申请号：AU5506690

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：CO4520299A1

公开(公告)日：1997-10-15

申请号：CO92302647

申请日：1989-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MARK E DEAN

IPC: G06F12/00 ,  G06F12/08

Abstract: REIVINDICACION NUMERO UN SISTEMA MICROCOMPUTADOR DE LINEAS MULTIPLES, QUE COMPRENDE: UN PROCESADOR 80386 Y UN SUBSISTEMA CACHE CONECTA- DOS ENTRE SI POR UNA LINEA LOCAL DEL CPU, COMPREN- DIENDO DICHO SUBSISTEMA CACHE UN CONTROLADOR CACHE 82385, Y UNA MEMORIA CACHE, Y MEDIOS LOGICOS QUE CONECTAN LAS SENALES DE CAPACI- TACION DE ESCRITURA, DESDE DICHO CONTROLADOR CACHE 82385 HASTA DICHA MEMORIA CACHE, COMPRENDIENDO DI- CHOS MEDIOS LOGICOS: a) MEDIOS LOGICOS DE RETARDO QUE RESPONDEN A UNA CONDICION DE ESCRITURA CACHE PRODUCIDA POR UNA PERDIDA DE LECTURA, Y QUE RESPONDEN A UNA SENAL DE SALIDA DE CAPACITACION DE ESCRITURA PROVENIENTE DEL DICHO CONTROLADOR CACHE 82385, Y QUE TIENE UN TERMINAL DE CAPACITACION DE ESCRITURA, PARA PRODU- CIR UNA SENAL RETARDADA DE CAPACITACION DE ESCRI- TURA, EN DICHO TERMINAL DE CAPACITACION DE ESCRI- TURA, b) UNA PUERTA LOGICA CON UNA PRIMERA ENTRADA ACO- PLADA A DICHA ENTRADA DE CAPACITACION DE ESCRITURA DE DICHO CONTROLADOR CACHE 82385, Y UNA SEGUNDA ENTRADA ACOPLADA A DICHO TERMINAL DE CAPACITACION DE ESCRITURA, Y UNA SALIDA ACOPLADA A UNA ENTRADA DE CAPACITACION DE ESCRITURA DE DICHA MEMORIA CA- CHE. 7. UN SISTEMA MICROCOMPUTADOR DE LINEA MULTIPLE CACHE 80386/82385 MEJORADO, PARA RETARDAR SELECTI- VAMENTE LAS SENALES DE ESCRITURA CACHE QUE SIGUEN A LA PERDIDA DE UNA LECTURA, PARA MEJORAR LA TOLE- RANCIA DEL SISTEMA A LOS COMPONENTES MAS LENTOS DE LA MEMORIA, SIN IMPACTAR LOS PARAMETROS DEL ESTADO DE ESPERA PARA OPERACIONES DE PERDIDAS DE LECTU- RAS, COMPRENDIENDO DICHO SISTEMA MICROPROCESADOR: UN SUBSISTEMA CACHE QUE INCLUYE UN CONTROLADOR CA- CHE 82385, UNA MEMORIA CACHE Y UNA LINEA LOCAL QUE CONECTA DICHO CONTROLADOR CACHE 82385 Y DICHA ME- MORIA CACHE, CON UN PROCESADOR 80386, Y... FIGURA 1

公开(公告)号：DE69029438T2

公开(公告)日：1997-06-12

申请号：DE69029438

申请日：1990-06-11

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F13/36 ,  G06F12/00 ,  G06F12/02 ,  G06F13/28 ,  G06F13/42 ,  G06F13/38 ,  G06F9/00

Abstract: A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode.

公开(公告)号：PH30403A

公开(公告)日：1997-05-08

申请号：PH40588

申请日：1990-05-30

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F13/00

公开(公告)号：PH30307A

公开(公告)日：1997-03-06

申请号：PH40475

申请日：1990-05-03

Applicant: IBM

Inventor： BEGUN RALPH M ,  DEAN MARK E ,  BLAND PATRICK M

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：PT90632B

公开(公告)日：1995-12-29

申请号：PT9063289

申请日：1989-05-23

Applicant: IBM

Inventor： BLAND PATRICK MAURICE ,  BEGUN RALPH M ,  DEAN MARK E

IPC: G06F12/08

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.