中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

44 records (took 0.019 seconds)

    System for authentication of i2c bus transactions, computer program and method
    1.
    发明专利
    System for authentication of i2c bus transactions, computer program and method 审中-公开
    I2C总线交易认证系统，计算机程序和方法

    公开(公告)号：JP2007174628A

    公开(公告)日：2007-07-05

    申请号：JP2006302018

    申请日：2006-11-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： BANDHOLZ JUSTIN POTOK ,  BEGUN RALPH M ,  HEINZMANN ANDREW S ,  LOPEZ FERNANDO A

    IPC: H04L9/32 ,  G09C1/00

    CPC classification number: G06F21/85 ,  H04L9/3236

    Abstract: PROBLEM TO BE SOLVED: To provide a function for authenticating a communication occurring on an I
    2 C bus and guaranteeing the correctness of the communication.
    SOLUTION: Authenticated communication (transaction) is enabled on a standard I
    2 C bus without requiring modification of existing I
    2 C devices. Read and write transactions occurring on the bus are authenticated using an Authentication Agent and a shared secret key. In addition to allowing verification of the legitimacy of the transactions, the authentication of the I
    2 C transactions enhances the reliability and serviceability of the bus and devices on the bus by allowing the Baseboard Management Controller (BMC) to quickly determine errors and specify it.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供用于认证在I 2 C总线上发生的通信并保证通信的正确性的功能。

    解决方案：在标准I 2 C总线上启用认证通信（事务），而不需要修改现有的I 2 C设备。 总线上发生的读写事务使用认证代理和共享密钥进行身份验证。 除了允许验证交易的合法性之外，I 2 C事务的认证通过允许基板管理控制器（BMC）到总线和设备的总线和设备的可靠性和可服务性， 快速确定错误并指定。 版权所有（C）2007，JPO＆INPIT

    3.
    发明专利
    未知

    公开(公告)号：DE69029438D1

    公开(公告)日：1997-01-30

    申请号：DE69029438

    申请日：1990-06-11

    Applicant: IBM

    Inventor： BEGUN RALPH M

    IPC: G06F13/36 ,  G06F12/00 ,  G06F12/02 ,  G06F13/28 ,  G06F13/42 ,  G06F13/38 ,  G06F9/00

    Abstract: A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode.

    CONTROL OF PIPELINED OPERATION IN A MICROCOMPUTER SYSTEM EMPLOYING DYNAMIC BUS SIZING WITH 80386 PROCESSOR AND 82385 CACHE CONTROLLER
    5.
    发明专利
    CONTROL OF PIPELINED OPERATION IN A MICROCOMPUTER SYSTEM EMPLOYING DYNAMIC BUS SIZING WITH 80386 PROCESSOR AND 82385 CACHE CONTROLLER 未知

    公开(公告)号：CA1313274C

    公开(公告)日：1993-01-26

    申请号：CA597893

    申请日：1989-04-26

    Applicant: IBM

    Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

    IPC: G06F9/38 ,  G06F12/08

    Abstract: BC988-005 CONTROL OF PIPELINED OPERATION IN A MICROCOMPUTER SYSTEM EMPLOYING DYNAMIC BUS SIZING WITH 80386 PROCESSOR AND 82385 CACHE CONTROLLER Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for noncacheable devices are not in that predetermined range. Since by definition cacheable devices are 32bit devices, pipelined operation is allowed only in the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are noncacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining. The invention further provides for proper interface between a DMA mechanism (driven by a first clock) and a CPU local bus subsystem (driven by an entirely different clock). Data provided by the DMA mechanism is latched into an interface between the CPU local bus and the system bus, and a DMA cycle completed. Only after completion of the DMA cycle is detected, is the cycle on the CPU local bus allowed to BC988-005 33 complete. In this fashion, the CPU can go on to a following operation and be assured that the DMA mechanism is no longer driving the system bus.

    6.
    发明专利
    未知

    公开(公告)号：IT1230190B

    公开(公告)日：1991-10-18

    申请号：IT2062589

    申请日：1989-05-24

    Applicant: IBM

    Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

    IPC: G06F12/08 ,  G06F

    Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

    DUAL BUS MICROCOMPUTER SYSTEM WITH PROGRAMMABLE CONTROL OF LOCK FUNCTION
    8.
    发明专利
    DUAL BUS MICROCOMPUTER SYSTEM WITH PROGRAMMABLE CONTROL OF LOCK FUNCTION 未知

    公开(公告)号：CA2016400A1

    公开(公告)日：1990-11-30

    申请号：CA2016400

    申请日：1990-05-09

    Applicant: IBM

    Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

    IPC: G06F12/08

    Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

    9.
    发明专利
    未知

    公开(公告)号：PT90632A

    公开(公告)日：1989-11-30

    申请号：PT9063289

    申请日：1989-05-23

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  BEGUN RALPH M ,  DEAN MARK E

    IPC: G06F12/08 ,  G06F

    Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

Patent Agency Ranking