公开(公告)号：CA1317682C

公开(公告)日：1993-05-11

申请号：CA597890

申请日：1989-04-26

Applicant: IBM

Inventor： BLAND PATRICK M ,  DEAN MARK E ,  MILLING PHILIP E

IPC: G06F9/44 ,  G06F9/445 ,  G06F13/36 ,  G06F13/362 ,  G06F13/20 ,  G06F13/16

Abstract: BC988-004 SYSTEM BUS PREEMPT FOR 80386 WHEN RUNNING IN AN 8036/82385 MICROCOMPUTER SYSTEM WITH ARBITRATION A multi-bus microcomputer system includes a cache subsystem and an arbitration supervisor. A CPU is provided with a PREEMPT signal source which generates a preempt signal in CPU cycles extending beyond a specified duration. The preempt signal is effective at any device having access to the bus to initiate an orderly termination or the bus usage. When that device signals its termination of bus usage, the arbitration supervisor changes the state or an ARB/GRANT conductor, which had been in the grant phase, to the arbitration phase. During the arbitration phase each of the devices (other than the CPU) cooperates in an arbitration mechanism for bus usage during the next grant phase. On the other hand, the CPU, having asserted preempt, responds to a signal indicating initiation or the arbitration phase by immediately accessing the system bus.

公开(公告)号：CA1313274C

公开(公告)日：1993-01-26

申请号：CA597893

申请日：1989-04-26

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F9/38 ,  G06F12/08

Abstract: BC988-005 CONTROL OF PIPELINED OPERATION IN A MICROCOMPUTER SYSTEM EMPLOYING DYNAMIC BUS SIZING WITH 80386 PROCESSOR AND 82385 CACHE CONTROLLER Any incompatibility between pipelined operations (such as is available in the 80386) and dynamic bus sizing (allowing the processor to operate with devices of 8-, 16- and 32-bit sizes) is accommodated by use of an address decoder and ensuring that device addresses for cacheable devices are in a first predetermined range and any device addresses for noncacheable devices are not in that predetermined range. Since by definition cacheable devices are 32bit devices, pipelined operation is allowed only in the address decoder indicates the access is to a cacheable device. In that event, a next address signal is provided to the 80386. This allows the 80386 to proceed to a following cycle prior to completion of the previous cycle. For accesses which are to devices whose address indicate they are noncacheable, a next address signal is withheld until the cycle is completed, i.e. without pipelining. The invention further provides for proper interface between a DMA mechanism (driven by a first clock) and a CPU local bus subsystem (driven by an entirely different clock). Data provided by the DMA mechanism is latched into an interface between the CPU local bus and the system bus, and a DMA cycle completed. Only after completion of the DMA cycle is detected, is the cycle on the CPU local bus allowed to BC988-005 33 complete. In this fashion, the CPU can go on to a following operation and be assured that the DMA mechanism is no longer driving the system bus.

公开(公告)号：CA2051175A1

公开(公告)日：1992-04-02

申请号：CA2051175

申请日：1991-09-11

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL C ,  BLAND PATRICK M ,  STUTES RODGER M

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：IT1230190B

公开(公告)日：1991-10-18

申请号：IT2062589

申请日：1989-05-24

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/08 ,  G06F

Abstract: A microcomputer system includes a microprocessor, a cache memroy, and a cache controller all coupled to a local bus. The local bus is coupled to a sytem bus, connecting the remaining system components, through latches. When writing data, the microcomputer can perform a posted write to a unit on the system bus by writing the data into the latches and then, on receipt of a ready signal from the cache controller, continuing its operations without waiting for the data to pas to its destination. A problem arises if the data is posted to a unit with a data width less than that of the microprocessor. In this case, the data should be sent in multiple cycles, but the read signal is generated before the data width of the unit is known and the microprocessor then continues its operations and can not, therefore, transmit the data correctly. To solve this problem, a logic unit is added to monitor the ready signal and the output of a decoder which detects non-cacheable addresses (which are of data width different from the microprocessor data width). If a non-cacheable address is detected, the read signal from the cache controller through the logic unit is withheld from the microprocessor, which now waits to continue processing beyond the write until a ready signal is received from the addressed unit on the system bus.

公开(公告)号：CA2016400A1

公开(公告)日：1990-11-30

申请号：CA2016400

申请日：1990-05-09

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：PH30402A

公开(公告)日：1997-05-08

申请号：PH38469

申请日：1989-04-10

Applicant: IBM

Inventor： BLAND PATRICK M ,  DEAN MARK E

IPC: G06F13/36 ,  G11C11/401 ,  G06F13/362 ,  G11C7/10 ,  G06F7/00

Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

公开(公告)号：CA2160499A1

公开(公告)日：1996-05-31

申请号：CA2160499

申请日：1995-10-13

Applicant: IBM

Inventor： BLAND PATRICK M ,  CRONIN DANIEL R III ,  HOFMANN RICHARD G ,  MOELLER DENNIS ,  VENARCHICK LANCE M

IPC: G06F12/06 ,  G06F13/28 ,  G06F13/36 ,  G06F13/40 ,  G06F12/02

Abstract: A computer system that has two buses with different memory addressing capacitiesand a first bus master that generates M-bit addresses is provided with a bridge between the two buses. In order to generate N-bit addresses for use on the second bus, a direct memory access (DMA) controller on the bridge produces P bits, where P + M = N. The P bits are concentrated with the M bits to form an N-bit address used on the second bus to address memory. The addition of P bits reallocates the memory segment addressable by the M-bits to any location within the memory map addressable by an N-bit address.

公开(公告)号：NZ233538A

公开(公告)日：1992-06-25

申请号：NZ23353890

申请日：1990-05-02

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08 ,  G06F13/16

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：BR9002555A

公开(公告)日：1991-08-13

申请号：BR9002555

申请日：1990-05-30

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08 ,  G06F15/20

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：AU5506690A

公开(公告)日：1990-12-06

申请号：AU5506690

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.