公开(公告)号：MY118417A

公开(公告)日：2004-10-30

申请号：MYPI20001067

申请日：2000-03-17

Applicant: IBM

Inventor： BEALOWSKI RICHARD ,  BLAND PATRICK M

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/50 ,  G06F15/16

Abstract: A SYSTEM FOR PARTITIONING AND ALLOCATING INDIVIDUAL PCI SLOTS WITHIN A PRIMARY HOST BRIDGE (PHB) IN A PARTITIONED COMPUTER SYSTEM IS PROVIDED. AN INNOVATIVE PHB SYSTEM IS INCLUDED WHICH ALLOWS A PCI SLOT TO BE DYNAMICALLY ASSIGNED TO ONE OR MORE PARTITIONS AT A GIVEN TIME, ALLOWING FOR MORE EFFICIENT ALLOCATION OF SYSTEM RESOURCES. (FIGURE 1)

公开(公告)号：CA2298783A1

公开(公告)日：2000-09-30

申请号：CA2298783

申请日：2000-02-16

Applicant: IBM

Inventor： BLAND PATRICK M ,  BEALKOWSKI RICHARD

IPC: G06F13/14 ,  G06F13/38 ,  H04L12/44 ,  H04L12/02 ,  H04L12/28

Abstract: A system and method for providing network communications between personal computer systems using USB communications. The disclosed USB networking hub allows multiple hosts to exist in a USB-based network. The networking hub includes an integrated virtual network adapter, which provides for communications among and between multiple hosts.

公开(公告)号：CO4520299A1

公开(公告)日：1997-10-15

申请号：CO92302647

申请日：1989-05-16

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MARK E DEAN

IPC: G06F12/00 ,  G06F12/08

Abstract: REIVINDICACION NUMERO UN SISTEMA MICROCOMPUTADOR DE LINEAS MULTIPLES, QUE COMPRENDE: UN PROCESADOR 80386 Y UN SUBSISTEMA CACHE CONECTA- DOS ENTRE SI POR UNA LINEA LOCAL DEL CPU, COMPREN- DIENDO DICHO SUBSISTEMA CACHE UN CONTROLADOR CACHE 82385, Y UNA MEMORIA CACHE, Y MEDIOS LOGICOS QUE CONECTAN LAS SENALES DE CAPACI- TACION DE ESCRITURA, DESDE DICHO CONTROLADOR CACHE 82385 HASTA DICHA MEMORIA CACHE, COMPRENDIENDO DI- CHOS MEDIOS LOGICOS: a) MEDIOS LOGICOS DE RETARDO QUE RESPONDEN A UNA CONDICION DE ESCRITURA CACHE PRODUCIDA POR UNA PERDIDA DE LECTURA, Y QUE RESPONDEN A UNA SENAL DE SALIDA DE CAPACITACION DE ESCRITURA PROVENIENTE DEL DICHO CONTROLADOR CACHE 82385, Y QUE TIENE UN TERMINAL DE CAPACITACION DE ESCRITURA, PARA PRODU- CIR UNA SENAL RETARDADA DE CAPACITACION DE ESCRI- TURA, EN DICHO TERMINAL DE CAPACITACION DE ESCRI- TURA, b) UNA PUERTA LOGICA CON UNA PRIMERA ENTRADA ACO- PLADA A DICHA ENTRADA DE CAPACITACION DE ESCRITURA DE DICHO CONTROLADOR CACHE 82385, Y UNA SEGUNDA ENTRADA ACOPLADA A DICHO TERMINAL DE CAPACITACION DE ESCRITURA, Y UNA SALIDA ACOPLADA A UNA ENTRADA DE CAPACITACION DE ESCRITURA DE DICHA MEMORIA CA- CHE. 7. UN SISTEMA MICROCOMPUTADOR DE LINEA MULTIPLE CACHE 80386/82385 MEJORADO, PARA RETARDAR SELECTI- VAMENTE LAS SENALES DE ESCRITURA CACHE QUE SIGUEN A LA PERDIDA DE UNA LECTURA, PARA MEJORAR LA TOLE- RANCIA DEL SISTEMA A LOS COMPONENTES MAS LENTOS DE LA MEMORIA, SIN IMPACTAR LOS PARAMETROS DEL ESTADO DE ESPERA PARA OPERACIONES DE PERDIDAS DE LECTU- RAS, COMPRENDIENDO DICHO SISTEMA MICROPROCESADOR: UN SUBSISTEMA CACHE QUE INCLUYE UN CONTROLADOR CA- CHE 82385, UNA MEMORIA CACHE Y UNA LINEA LOCAL QUE CONECTA DICHO CONTROLADOR CACHE 82385 Y DICHA ME- MORIA CACHE, CON UN PROCESADOR 80386, Y... FIGURA 1

公开(公告)号：PH30307A

公开(公告)日：1997-03-06

申请号：PH40475

申请日：1990-05-03

Applicant: IBM

Inventor： BEGUN RALPH M ,  DEAN MARK E ,  BLAND PATRICK M

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：CA1314330C

公开(公告)日：1993-03-09

申请号：CA597891

申请日：1989-04-26

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/08 ,  G06F13/20

Abstract: BC988-003 METHOD AND APPARATUS FOR SELECTIVELY POSTING WRITE CYCLES USING THE 82385 CACHE CONTROLLER A microcomputer system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion or an address asserted on a CPU local bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

公开(公告)号：CA1314103C

公开(公告)日：1993-03-02

申请号：CA597892

申请日：1989-04-26

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/08 ,  G06F13/16 ,  G06F13/38

Abstract: BC388-G06 DELAYED CACHE WRITE ENABLE CIRCUIT FOR A DUAL BUS MICROCOMPUTER SYSTEM WITH AN 80386 AND 82385 In an 80386/82385 microcomputer system, the timing requirements placed on non-cache memory components by the 82385 are more stringent than the timing requirements placed on the non-cache memory components by the 80386. The present invention operates on the 82385 cache write enable (CWE) signals, and delays those signals in the event of a read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cacne memory components and at the same time does not impact wait state parameters for read miss operations.

公开(公告)号：AU627304B2

公开(公告)日：1992-08-20

申请号：AU5506090

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：DD295261A5

公开(公告)日：1991-10-24

申请号：DD34178290

申请日：1990-06-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F13/14

公开(公告)号：AU5506090A

公开(公告)日：1990-12-06

申请号：AU5506090

申请日：1990-05-15

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：CA2299547A1

公开(公告)日：2000-09-30

申请号：CA2299547

申请日：2000-02-25

Applicant: IBM

Inventor： BLAND PATRICK M ,  BEALKOWSKI RICHARD

IPC: G06F13/14 ,  G06F9/46 ,  G06F9/50 ,  G06F15/16 ,  G06F15/17

Abstract: A system for partitioning and allocating individual PCI slots within a Primary Host Bridge (PHB) in a partitioned computer system is provided. An innovative PHB system is included which allows a PCI slot to be dynamically assigned to one or more partitions at a given time, allowing for more efficient allocation of system resources.