中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

187 records (took 0.036 seconds)

    12.
    发明专利
    未知

    公开(公告)号：ES2063818T3

    公开(公告)日：1995-01-16

    申请号：ES89305306

    申请日：1989-05-25

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F9/38 ,  G06F12/08

    Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

    13.
    发明专利
    未知

    公开(公告)号：NO175837C

    公开(公告)日：1994-12-14

    申请号：NO891583

    申请日：1989-04-18

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F12/08 ,  G06F12/06 ,  G06F13/38

    Abstract: In a dual bus microcomputer system using a cache memory and a cache controller, the timing requirements placed on non-cache memory components by the cache controller are more stringent than the timing requirements placed on the non-cache memory components by the microprocessor. A logic circuit operates on the cache write enable (CWE) signals, and delays those signals in the event of a cache read miss. Delaying the CWE signals relaxes the timing requirements placed on non-cache memory components and at the same time does not impact wait state parameters for read miss operations.

    14.
    发明专利
    未知

    公开(公告)号：DE68918754D1

    公开(公告)日：1994-11-17

    申请号：DE68918754

    申请日：1989-05-25

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F9/38 ,  G06F12/08

    Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

    15.
    发明专利
    未知

    公开(公告)号：AT112869T

    公开(公告)日：1994-10-15

    申请号：AT89305306

    申请日：1989-05-25

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F9/38 ,  G06F12/08

    Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

    16.
    发明专利
    未知

    公开(公告)号：MX167244B

    公开(公告)日：1993-03-11

    申请号：MX1614189

    申请日：1989-05-22

    Applicant: IBM

    Inventor： BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F13/36 ,  G11C11/401 ,  G06F13/362 ,  G11C7/10 ,  G06F7/00

    Abstract: A computer system includes a page memory in which a row address accompanied by a row address strobe (RAS) is followed by a column address accompanied by a column address strobe (CAS) to read data from a memory location during a memory cycle. When, in a following memory cycle, a further location from the same page is to be accessed, the row address and the RAS remain constant and a new column address is used with the CAS being precharged by switching it to its OFF state and then returning it to its ON state. This is normally done at the start of the following memory cycle. In the present system, the data is read and latched shortly after arrival of the column address and CAS in the first of the memory cycles so that the CAS recharge can take place at the end of the first memory cycle and before the start of the following memory cycle.

    18.
    发明专利
    未知

    公开(公告)号：IT1230207B

    公开(公告)日：1991-10-18

    申请号：IT2064889

    申请日：1989-05-25

    Applicant: IBM

    Inventor： BEGUN RALPH MURRAY ,  BLAND PATRICK MAURICE ,  DEAN MARK EDWARD

    IPC: G06F9/38 ,  G06F12/08 ,  G06F

    Abstract: In a microcomputer system comprising a microprocessor and a cache subsystem and operable in a pipelined mode, there is potential incompatibility between pipelined operations and dynamic bus sizing as the cache subsystem operates with a fixed size data width and dynamic bus sizing allows the system to operate with devices of differing data width. This incompatibility is accommodated by the present system by defining certain addresses as cacheable addresses and other addresses as non-cacheable addresses and ensuring that addresses of devices of data width different from the cache data width are non-cacheable. An address decoder provides a control signal indicating whether or not a generated address is within the cacheable range. This control signal controls a next address signal applied to the microprocessor, which signal allows the processor to proceed to a following cycle prior to the end of the current cycle. Whenever a non-cacheable address is detected, the next address signal is suppressed.

    19.
    发明专利
    未知

    公开(公告)号：FI914608A0

    公开(公告)日：1991-10-01

    申请号：FI914608

    申请日：1991-10-01

    Applicant: IBM

    Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

    IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G11C

    Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

Patent Agency Ranking