公开(公告)号：FI914608A

公开(公告)日：1992-04-02

申请号：FI914608

申请日：1991-10-01

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G11C

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：NO913799D0

公开(公告)日：1991-09-27

申请号：NO913799

申请日：1991-09-27

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：DE69132539D1

公开(公告)日：2001-03-29

申请号：DE69132539

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G06F12/06 ,  G11C8/12

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

公开(公告)号：IN179339B

公开(公告)日：1997-09-27

申请号：IN110MA1991

申请日：1991-02-11

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G06F7/00 ,  G06F15/00

公开(公告)号：DE69124905D1

公开(公告)日：1997-04-10

申请号：DE69124905

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  BLAND PATRICK MAURICE ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：FI914608A0

公开(公告)日：1991-10-01

申请号：FI914608

申请日：1991-10-01

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G11C

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：SG44436A1

公开(公告)日：1997-12-19

申请号：SG1996000370

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGULA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：AU652570B2

公开(公告)日：1994-09-01

申请号：AU8345291

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：AU8345391A

公开(公告)日：1992-04-09

申请号：AU8345391

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G06F12/06 ,  G11C8/12 ,  G06F13/14

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

公开(公告)号：NO913799L

公开(公告)日：1992-04-02

申请号：NO913799

申请日：1991-09-27

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.