公开(公告)号：WO2007110329A2

公开(公告)日：2007-10-04

申请号：PCT/EP2007052411

申请日：2007-03-14

Applicant: IBM ,  IBM UK ,  ALDEREGUIA ALFREDO ,  RICHTER GRACE ANN ,  WILLIAMS JEFFREY

Inventor： ALDEREGUIA ALFREDO ,  RICHTER GRACE ANN ,  WILLIAMS JEFFREY

IPC: H04L12/26

CPC classification number: H04L43/50 ,  H04L43/0823 ,  H04L43/0829 ,  H04L43/16

Abstract: An apparatus, system, and method are disclosed for assessing error over a communication link. The apparatus for assessing error is provided with a logic unit containing a plurality of modules configured to execute the necessary steps of creating one or more test packets, determining an amount of test packets to send over a communication link to a receiving node, sending a plurality of test packets over the communication link to a receiving node, interspersing test packets throughout a plurality of data packets such that the receiving node is able to continually process the data packets, and checking test packets received by the receiving node for errors.

Abstract translation: 公开了一种用于评估通信链路上的错误的设备，系统和方法。 用于评估错误的装置具有包含多个模块的逻辑单元，所述多个模块被配置为执行创建一个或多个测试分组，确定通过通信链路发送到接收节点的测试分组的数量，发送多个 通过通信链路将测试分组传送到接收节点，将测试分组穿插到整个多个数据分组中，使得接收节点能够连续地处理数据分组，并且检查接收节点接收到的测试分组是否有错误。

公开(公告)号：WO2007110329B1

公开(公告)日：2008-03-20

申请号：PCT/EP2007052411

申请日：2007-03-14

Applicant: IBM ,  IBM UK ,  ALDEREGUIA ALFREDO ,  RICHTER GRACE ANN ,  WILLIAMS JEFFREY

Inventor： ALDEREGUIA ALFREDO ,  RICHTER GRACE ANN ,  WILLIAMS JEFFREY

IPC: H04L12/26

CPC classification number: H04L43/50 ,  H04L43/0823 ,  H04L43/0829 ,  H04L43/16

Abstract: An apparatus, system, and method are disclosed for assessing error over a communication link. The apparatus for assessing error is provided with a logic unit containing a plurality of modules configured to execute the necessary steps of creating one or more test packets, determining an amount of test packets to send over a communication link to a receiving node, sending a plurality of test packets over the communication link to a receiving node, interspersing test packets throughout a plurality of data packets such that the receiving node is able to continually process the data packets, and checking test packets received by the receiving node for errors.

Abstract translation: 公开了一种用于评估通信链路上的错误的装置，系统和方法。 提供了用于评估错误的装置，该逻辑单元包括多个模块，该多个模块被配置为执行创建一个或多个测试分组的必要步骤，确定通过通信链路发送到接收节点的测试分组的量，发送多个 通过通信链路将测试数据包发送到接收节点，在多个数据分组中散布测试分组，使得接收节点能够连续地处理数据分组，并且检查由接收节点收到的测试分组的错误。

公开(公告)号：JP2007013980A

公开(公告)日：2007-01-18

申请号：JP2006179451

申请日：2006-06-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ALDEREGUIA ALFREDO ,  RICHTER GRACE ANN ,  JEFFREY B WILLIAMS

IPC: H04L1/22 ,  H04L29/14

CPC classification number: G06F11/2007 ,  H04L1/0063 ,  H04L1/1803 ,  H04L1/22

Abstract: PROBLEM TO BE SOLVED: To provide a system and method for providing packet delivery that is guaranteed by a redundant path and an error checking process while communication signal lines between nodes are suppressed to a minimum.
SOLUTION: The redundant communication system and method for providing data communication between a first computing node and a second computing node are as follows. A transmitter is provided as a part of the first computing node. A receiver is provided as a part of the second computing node. A first signal line transmits a first data signal. The first signal line electrically connects the transmitter to the receiver. A second signal line transmits a second data signal which is redundant with respect to the first data signal. The second signal line electrically connects the transmitter to the receiver. The receiver checks the first data signal to determine if there is any error, and if an error is detected in the first data signal, the second node uses the second data signal.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于提供由冗余路径和错误检查过程保证的分组传送的系统和方法，同时将节点之间的通信信号线抑制到最小。 解决方案：用于在第一计算节点和第二计算节点之间提供数据通信的冗余通信系统和方法如下。 作为第一计算节点的一部分提供发射机。 作为第二计算节点的一部分提供接收机。 第一信号线发送第一数据信号。 第一个信号线将发射器电连接到接收器。 第二信号线发送相对于第一数据信号是冗余的第二数据信号。 第二信号线将发射器电连接到接收器。 接收机检查第一数据信号以确定是否存在任何错误，并且如果在第一数据信号中检测到错误，则第二节点使用第二数据信号。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007171166A

公开(公告)日：2007-07-05

申请号：JP2006301970

申请日：2006-11-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ALDEREGUIA ALFREDO ,  BAKER MARCUS A ,  BANDHOLZ JUSTIN POTOK ,  WILLIAMS JEFFREY BUCHANAN

IPC: G01R31/28 ,  G06F1/04 ,  G06F13/00

CPC classification number: G11B20/10009

Abstract: PROBLEM TO BE SOLVED: To provide a reception processor that is constituted, using a normal (operation) path and a testing path.
SOLUTION: The test path is constituted in parallel to the normal path. The test path simulates the data same to that of the normal path as an input to be received, and the test path has an individual voltage reference V
ref_test applied in a test input buffer. The same data input into the normal path is also input to the test buffer. The output from the test buffer is input to a test latch. A clock signal supplied to the test latch is a variable clock signal, capable of skewing selectively the clock signal. The output from the test latch is compared with the output from a normal latch, and the difference between the two output signals defines errors in a specified voltage/clock-skew combination.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供使用正常（操作）路径和测试路径构成的接收处理器。

解决方案：测试路径与正常路径平行。 测试路径将模拟与正常路径相同的数据作为要接收的输入，并且测试路径具有应用于测试输入缓冲器中的单独的参考电压V SBC ref_test 。 与正常路径相同的数据输入也输入到测试缓冲区。 测试缓冲区的输出被输入到测试锁存器。 提供给测试锁存器的时钟信号是可变时钟信号，能够选择性地倾斜时钟信号。 将测试锁存器的输出与正常锁存器的输出进行比较，两个输出信号之间的差定义了指定电压/时钟偏移组合的误差。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：FI914608A

公开(公告)日：1992-04-02

申请号：FI914608

申请日：1991-10-01

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G11C

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：NZ245346A

公开(公告)日：1995-09-26

申请号：NZ24534692

申请日：1992-12-02

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  AMINI NADER ,  HORNE RICHARD LOUIS ,  LOHMAN TERENCE JOSEPH ,  TRAN CANG NGOC

IPC: G06F13/16 ,  G06F13/36 ,  G06F15/76

Abstract: A computer system is provided, comprising system memory and a memory controller for controlling access to system memory, a central processing unit electrically connected with the memory controller, and a bus interface unit electrically connected to the memory controller by a system bus and electrically connected to an input/output device by an input/output bus. The bus interface unit includes translation logic for temporarily storing, in response to a predetermined set of operating conditions, data transferred between the system bus and the input/output bus through the bus interface unit. The predetermined set of operating conditions occur when (i) the memory controller on behalf of the central processing unit writes data to the input/output device, or (ii) the memory controller on behalf of the central processing unit initiates a read or write cycle destined for the input/output device acting as a slave on the input/output bus, and the data bus width of the memory controller is greater than a corresponding data bus width of the input/output device.

公开(公告)号：AU652570B2

公开(公告)日：1994-09-01

申请号：AU8345291

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：BR9104142A

公开(公告)日：1992-06-02

申请号：BR9104142

申请日：1991-09-26

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL C ,  STUTES ROGER M

IPC: G06F12/06 ,  G11C8/12 ,  G06F13/16 ,  G11C8/00

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

公开(公告)号：AU8345391A

公开(公告)日：1992-04-09

申请号：AU8345391

申请日：1991-08-30

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G06F12/06 ,  G11C8/12 ,  G06F13/14

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

公开(公告)号：NO913799L

公开(公告)日：1992-04-02

申请号：NO913799

申请日：1991-09-27

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  BLAND PATRICK MAURICE ,  CROMER DARYL CARVIS ,  STUTES ROGER MAX

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.