公开(公告)号：US3705357A

公开(公告)日：1972-12-05

申请号：US3705357D

申请日：1971-03-23

Applicant: IBM

Inventor： CARTER WILLIAM C ,  JESSEP DONALD C JR ,  WADIA ASPI B

IPC: G06F11/16 ,  H03K19/32 ,  H03K19/38

CPC classification number: H03K19/007

Abstract: The present invention relates to a logic circuit for testing the condition of a set of self-testing logic variables. More specifically, it relates to such a logic circuit for forming an Exclusive-Or function on such variables. The circuit has particular utility in high reliability systems for checking the conditions of a plurality of line pairs wherein each line pair constitutes a morphic self-testing variable and wherein the circuit output is itself a morphic self-testing function.

公开(公告)号：US3688265A

公开(公告)日：1972-08-29

申请号：US3688265D

申请日：1971-03-18

Applicant: IBM

Inventor： CARTER WILLIAM C ,  HENLE ROBERT A ,  JESSEP DONALD C JR ,  WADIA ASPI B

IPC: G06F11/10 ,  G06F11/267 ,  G08C25/00 ,  G06F11/00

CPC classification number: G06F11/1044 ,  G06F11/2215

Abstract: A translator for a digital memory system which performs single error correction and double error detection (SEC/DED) upon the stored word in converting it into a parity-encoded form and in addition detects circuit failures in the translator itself. The translator also takes a parity-encoded word, checks the parity encoding, translates the word into an SEC/DED form and writes it into memory. The translator consists of a syndrome generator, a single error corrector, a double error detector, a byte parity encoder, a byte parity checker and a circuit to implement a check on the parity-encoded form of the word which is read. The paritycheck matrix used in formulating the SEC/DED encoded form of the word has the following properties: Property 1: The columns of the parity check matrix are a minimum Hamming distance of 2 apart. Property 2: Each column of the parity check matrix is odd weight. Property 3: If there are r check bits C(j), m bytes with parity bits P(i), and odd parity is used, then

Abstract translation: 一种用于数字存储器系统的翻译器，其对存储的字执行单个纠错和双重错误检测（SEC / DED），将其转换为奇偶校验编码形式，并且还检测翻译器本身中的电路故障。 翻译器还采用奇偶校验编码的字，检查奇偶编码，将该字翻译成SEC / DED格式，并将其写入内存。 翻译器由校正子发生器，单个误差校正器，双重误差检测器，字节奇偶编码器，字节奇偶校验器和用于对读取的字的奇偶校验编码形式进行检查的电路组成。 用于制定SEC / DED编码形式的奇偶校验矩阵具有以下属性：

公开(公告)号：US3665175A

公开(公告)日：1972-05-23

申请号：US3665175D

申请日：1968-09-03

Applicant: IBM

Inventor： BOURICIUS WILLARD G ,  CARTER WILLIAM C ,  ROTH JOHN P ,  SCHNEIDER PETER R

IPC: G11C29/00

CPC classification number: G11C29/76

Abstract: Mapping control means for achieving error toleration in computer addressing circuitry including switching means for connecting an address register with the effective address register of a basic operating module. The switching means are operable by a blocking register and at least one status register to control the mapping connections in a given manner. The invention is characterized by the provision of an address blocking register and a mask register that process a sequence of failed addresses and insert corresponding control instructions in the blocking and status registers so that the switching means dynamically excludes access to the memory area affected by the faulty address circuitry.

公开(公告)号：US3634665A

公开(公告)日：1972-01-11

申请号：US3634665D

申请日：1969-06-30

Applicant: IBM

Inventor： CARTER WILLIAM C ,  SCHNEIDER PETER R

IPC: H03M13/00 ,  G06F11/16 ,  G06F11/20 ,  G06F11/22 ,  G06F15/16

CPC classification number: G01R31/31835 ,  G01R31/3187 ,  G06F11/1032

Abstract: A self-testing error-checking system for inclusion in a computer comprising a plurality of self-testing check circuits, each said circuit having a two-rail complementary output whenever both the circuits being tested and the checking circuit is operating properly and an identical output on each of the two output lines whenever a fault is detected. The improvement which comprises reduction checking means connected to all said two-rail outputs from said checking circuits, and means connected to the output of said reduction checker means for at least indicating that a failure has occurred. The output of said reduction checker itself is two rail and complementary when all inputs are correct and the checker itself is operating properly. The output of the present checking system may be connected to a computer interrupt circuit or to a visual logout means. Alternatively, the system output may be utilized to effect automatic self-repair.

Abstract translation: 一种用于包含在包括多个自测试检查电路的计算机中的自检错误检查系统，每当所述两个电路被测试且检查电路正常工作并且相同的输出时，每个所述电路具有双轨互补输出 每当检测到故障时，在两条输出线中的每一条上。 所述改进包括从所述检查电路连接到所有所述两轨输出的减小检查装置，以及连接到所述缩小检查装置的输出的装置，用于至少指示发生故障。 当所有输入正确并且检验器本身正常运行时，所述还原检查器本身的输出是两个轨道和互补的。 本检查系统的输出可以连接到计算机中断电路或视觉注销装置。 或者，可以利用系统输出来实现自动自修复。

公开(公告)号：US3559168A

公开(公告)日：1971-01-26

申请号：US3559168D

申请日：1968-07-25

Applicant: IBM

Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  SCHNEIDER PETER R

IPC: G06F11/08 ,  H03K13/32 ,  G08C25/00

CPC classification number: G06F11/085

Abstract: A SERIES OF SELF-CHECKING ERROR CHECKING CIRCUITS ARE DISCLOSED FOR CHECKING K-OUT-OF-N CODED DATA LINES. THE N LINES ARE BROKEN INTO TWO, PREFERABLY EQUAL, GROUPS. A LOGIC EQUATION IS DERIVED FOR EACH GROUP OF LINES WHEREBY, WITH ANY K-OUT-OF-N CODED DATA SIGNALS APPLIED TO THE INPUT, AT LEAST TWO COMPLEMENTARY OUTPUT SIGNALS ARE PRODUCED. ANY ERROR APPEARING IN THE RECEIVED CODE WILL BE INDICATED AS SUCH BY NON-COMPLEMENTARY OUTPUTS FROM

THE CHECKER IN THE OUTPUT OF THE CHECKER. MALFUNCTIONS OR FAILURES IN THE CHECKING CIRCUIT ARE CHECKED BY CERTAIN LEGITIMATE CODE SIGNALS WHICH SIMILARLY CAUSE AN ERROR REPRESENTATION IN NON-COMPLEMENTARY OUTPUTS AT THE OUTPUT OF THE CHECKER.

公开(公告)号：CA993999A

公开(公告)日：1976-07-27

申请号：CA167868

申请日：1973-03-28

Applicant: IBM

Inventor： CARTER WILLIAM C ,  HSIEH EDWARD P ,  WADIA ASPI B

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00

Abstract: Novel error correction and detection codes and self-checking translators therefor are disclosed. A first of these codes is a t b-adjacent bit group error correcting and t+d b-adjacent d-adjacent bit group error detecting code using a quantity of 2t+d groups of b check bits. This code with a b-bit BSM (basic storage module) memory organization is capable of correcting b-adjacent errors due to failures in any t basic storage modules, detecting b-adjacent errors due to failures in any t+d basic storage modules, and, because of the translator design, detecting with high probability b-adjacent errors in 2t+2d-1 storage modules where 1

公开(公告)号：CA886747A

公开(公告)日：1971-11-23

申请号：CA886747D

Applicant: IBM

Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  SCHNEIDER PETER R

公开(公告)号：FR2296916A1

公开(公告)日：1976-07-30

申请号：FR7537206

申请日：1975-11-28

Applicant: IBM

Inventor： CARTER WILLIAM C

IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  H03M13/00 ,  G11C29/00

Abstract: Apparatus for a digital memory system which performs single and double error detection and correction, as well as the detection of faults in the memory storage elements which do not produce errors in the data word stored therein. The data word is encoded in a specialized Hamming SEC/DED code and the apparatus generates syndromes and byte parity bits which are analyzed to detect both the presence and nature of the errors and faults. A parallel correction procedure is followed and the results thereof compared to prevent the erroneous correction of errors.

公开(公告)号：CA915815A

公开(公告)日：1972-11-28

申请号：CA915815D

Applicant: IBM

Inventor： SCHNEIDER PETER R ,  CARTER WILLIAM C

IPC: G06F11/16 ,  G06F11/20 ,  G06F15/16

公开(公告)号：CA886748A

公开(公告)日：1971-11-23

申请号：CA886748D

Applicant: IBM

Inventor： SCHNEIDER PETER R ,  CARTER WILLIAM C