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    Parity checked shift register counters
    2.
    发明授权
    Parity checked shift register counters 失效
    奇妙的检查移位寄存器计数器

    公开(公告)号：US3701892A

    公开(公告)日：1972-10-31

    申请号：US3701892D

    申请日：1970-12-17

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  SCHNEIDER PETER R

    IPC: G06F11/10 ,  H03K21/40

    CPC classification number: G06F11/10 ,  H03K21/40

    Abstract: The present invention relates to a family of parity-checked shift register counters having a counting period not determined by a power of 2 wherein the power is determined by the number of shift register stages. It will be apparent that the range of the counter is effected by the number of stages but not necessarily the actual count. The family of counters is further characterized in that either odd or even parity may be designed into the output pattern of said counter, which parity will be automatically maintained for all binary-bit patterns to produce. The family of counters is further characterized in that they require only N+6 logic circuits wherein there are N shift register stages, four 2input exclusive ORs and 2 N input AND circuits. The counters are also characterized in that they are self testing. That is, all components are tested for faults in normal operations.

    Abstract translation: 本发明涉及一种奇偶校验移位寄存器计数器系列，其具有不由2的功率确定的计数周期，其中功率由移位寄存器级的数量确定。 显而易见的是，计数器的范围是通过阶数来实现的，但不一定是实际计数。 计数器系列的特征还在于奇数或偶校验可被设计成所述计数器的输出模式，对于所有二进制位模式产生，奇偶校验将被自动维持。 计数器系列的特征还在于它们仅需要N + 6逻辑电路，其中存在N个移位寄存器级，四个2输入异或和2N输入与电路。 柜台的特点还在于自检。 也就是说，所有组件都在正常操作中测试故障。

    Error correction system for use with a rotational single-error correction, double-error detection hamming code
    3.
    发明授权
    Error correction system for use with a rotational single-error correction, double-error detection hamming code 失效
    错误校正系统，具有旋转单一错误校正，双重错误检测命令代码

    公开(公告)号：US3697949A

    公开(公告)日：1972-10-10

    申请号：US3697949D

    申请日：1970-12-31

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  JESSEP DONALD C JR

    IPC: G06F11/10 ,  G06F11/12

    CPC classification number: G06F11/1012

    Abstract: The present invention relates to a highly-efficient system for performing single-error correction when utilized with a memory system including a memory equipped with error-detection circuitry for use with rotationally-encoded, single-error correction, double-error detection Hamming coded data wherein said memory system circuitry includes means for developing syndrome bits, the patterns of which indicate faulty operation. Hardware is included for first identifying the specific byte which contains the error and still further hardware is provided to locate the particular bit which is erroneous. By efficient use of the rotational characteristic of the present coding scheme, correction is made only when necessary and only that hardware necessary to correct a single byte is provided in the correction circuitry.

    Abstract translation: 本发明涉及一种用于执行单一错误校正的高效系统，该系统与存储器系统一起使用，存储器系统包括配备有用于旋转编码的单错误校正，双错误检测汉明编码数据的错误检测电路的存储器 其中所述存储器系统电路包括用于开发校正子位的装置，其模式指示故障操作。 包括硬件，用于首先识别包含错误的特定字节，并且还提供进一步的硬件来定位错误的特定位。 通过有效利用当前编码方案的旋转特性，仅在必要时进行校正，并且仅在校正电路中提供校正单个字节所需的硬件。

    Self-checking error checker for parity coded data
    5.
    发明授权
    Self-checking error checker for parity coded data 失效
    自检错误检查器，用于奇偶校验数据

    公开(公告)号：US3602886A

    公开(公告)日：1971-08-31

    申请号：US3602886D

    申请日：1968-07-25

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  SCHNEIDER PETER R

    IPC: G06F11/10 ,  H03K13/34 ,  H03K5/18 ,  H04L1/10

    CPC classification number: G06F11/10

    Abstract: A series of self-checking error checking circuits are disclosed for checking conventional parity coded data lines. The data signal set includes any logical combination of binary ''''1''s'''' and ''''0''s'''' and at least one parity bit. The circuit comprises at least 2 exclusive OR tree circuits wherein each tree obtains its inputs from different input lines whereby complementing outputs are produced by the two tree circuits for any correct signal set and wherein the checker is error free. Any error in the data will cause the two outputs to be the same. Malfunctions or failures in the checking circuit are checked by certain legitimate code signals which similarly cause an error representation in the output of the checker.

    System for translating to and from single error correction-double error detection hamming code and byte parity code
    7.
    发明授权
    System for translating to and from single error correction-double error detection hamming code and byte parity code 失效
    用于转换和从单个错误校正双重错误检测的系统命令代码和字节奇偶性代码

    公开(公告)号：US3648239A

    公开(公告)日：1972-03-07

    申请号：US3648239D

    申请日：1970-06-30

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  JESSEP DONALD C JR

    IPC: G06F11/10 ,  G08C25/00 ,  G06F11/00

    CPC classification number: G06F11/1012 ,  G06F11/10

    Abstract: An SEC/DED error detection and data translation mechanism is described. By the use of unique circuit design features, the same logical circuitry is capable of automatically taking Hamming encoded data from memory and parity encoding same for transmission elsewhere in the system as well as forming the necessary syndromes for purposes of error detection and correction. The same circuitry is capable of receiving encoded data from elsewhere in the system, first checking for any parity error and, if parity is proper, will generate the necessary Hamming check bits for storing in the memory together with the data information. The disclosed circuitry, by means of the unique partitioning thereof, separates the error detection and correction functions. It also generates parity bits essentially in parallel with error detection after a memory read cycle with the result that the data is propagated through the correction circuitry only when a single data bit error is detected.

    Abstract translation: 描述了SEC / DED错误检测和数据转换机制。 通过使用独特的电路设计特征，相同的逻辑电路能够自动地将来自存储器和奇偶校验编码的Hamming编码数据从系统中的其他地方传输，并形成用于错误检测和校正的必要的校验子。 相同的电路能够从系统的其他地方接收编码的数据，首先检查任何奇偶校验错误，并且如果奇偶校验是正确的，则将产生用于与数据信息一起存储在存储器中的必要的汉明校验位。 通过其独特的划分，所公开的电路分离出错误检测和校正功能。 它还在存储器读取周期之后基本上与错误检测并行地生成奇偶校验位，结果是仅当检测到单个数据位错误时，数据被传播通过校正电路。

    Self-checking error checker for two-rail coded data
    8.
    发明授权
    Self-checking error checker for two-rail coded data 失效
    自检错误检查器，用于两轨编码数据

    公开(公告)号：US3559167A

    公开(公告)日：1971-01-26

    申请号：US3559167D

    申请日：1968-07-25

    Applicant: IBM

    Inventor： CARTER WILLIAM C ,  DUKE KEITH A ,  SCHNEIDER PETER R

    IPC: G06F11/16 ,  H03K13/22

    CPC classification number: H03K19/00392 ,  G06F11/10

    Abstract: A SERIES OF SELF-CHECKING ERROR CHECKING CIRCUITS ARE DISCLOSED FOR CHECKING TWO-RAIL LOGIC CODED DATA LINES. THE DATA LINES ARE ARRANGED AS N PAIRS OF TWO-RAIL GROUPS. ONE FORM OF THE CHECKER COMPRISES N-1 BASIC TWO OUTPUT BLOCKS CONNECTED IN A GENERAL TREE CONFIGURATION ACROSS THE TWO-RAIL DATA LINES. EACH OF SAID BASIC BLOCKS HAS TWO NORMALLY COMPLEMENTARY OUTPUT LINES AND THE LAST STAGE OF THE CHECKER IS A SINGLA BASIC BLOCK. IF AN INVAID CODE IS RECEIVED, THE TWO OUTPUTS WILL BE IDENTICAL. MALFUNCTIONS OR FAILURES IN THE CHECKING CIRCUIT ARE CHECKED BY CERTAIN LEGITIMATE CODE SIGNALS WHICH SIMILARLY CAUSE AN ERROR REPRESENTATION IN THE OUTPUT OF THE CHECKER WHEREBY BOTH OUTPUTS WILL BE IDENTICAL.

    APPARATUS FOR DETECTING AND CORRECTING ERRORS IN AN ENCODED MEMORY WORD
    9.
    发明专利
    APPARATUS FOR DETECTING AND CORRECTING ERRORS IN AN ENCODED MEMORY WORD 未知

    公开(公告)号：CA1059237A

    公开(公告)日：1979-07-24

    申请号：CA239392

    申请日：1975-11-12

    Applicant: IBM

    Inventor： CARTER WILLIAM C

    IPC: G06F12/16 ,  G06F11/10 ,  G06F11/16 ,  H03M13/00 ,  G06F11/12

    Abstract: APPARATUS FOR DETECTING AND CORRECTING ERRORS IN AN ENCODED MEMORY WORD Apparatus for a digital memory system which performs single and double error detection and correction, as well as the detection of faults in the memory storage elements which do not produce errors in the data word stored therein. The data word is in encoded in a specialized Hamming SEC/DED code and the apparatus generates syndromes and byte parity bits which are analyzed to detect both the presence and nature of the errors and faults. A parallel correction procedure is followed and the results thereof compared to prevent the erroneous correction of errors.

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