公开(公告)号：BR8906142A

公开(公告)日：1990-07-31

申请号：BR8906142

申请日：1989-12-04

Applicant: IBM

Inventor： CHANG ALBERT ,  ROGERS MARK DOUGLAS

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009

Abstract: Multiple external page table (XPT) structure geometries provide efficient organisation and management of paged, segmented virtual memory systems. First and second small XPT geometries are provided for file mapping of files of a predetermined size for code segments, and file mapping of files exceeding the predetermined size for process private segments, respectively. A large XPT geometry is for working storage segments containing shared library routines. A uniform addressing scheme accesses page state information for second small and large XPT geometries having root blocks. Selected XPT structure direct blocks are pre-allocated for large XPT structures for address ranges to be referenced to reduce page faults.

公开(公告)号：DE3855250T2

公开(公告)日：1996-11-21

申请号：DE3855250

申请日：1988-11-09

Applicant: IBM

Inventor： AUSLANDER MARC ALAN ,  CHANG ALBERT ,  MORGAN STEPHEN PAUL ,  O'QUIN JOHN THOMAS ,  O'QUIN JOHN CLAUDE

IPC: G06F3/06 ,  G06F12/00 ,  G06F17/30 ,  G06F9/44

公开(公告)号：DE3855250D1

公开(公告)日：1996-06-05

申请号：DE3855250

申请日：1988-11-09

Applicant: IBM

Inventor： AUSLANDER MARC ALAN ,  CHANG ALBERT ,  MORGAN STEPHEN PAUL ,  O'QUIN JOHN THOMAS ,  O'QUIN JOHN CLAUDE

IPC: G06F3/06 ,  G06F12/00 ,  G06F17/30 ,  G06F9/44

公开(公告)号：DE3889739D1

公开(公告)日：1994-07-07

申请号：DE3889739

申请日：1988-01-26

Applicant: IBM

Inventor： CHANG ALBERT ,  SHAHEEN-GOUDA AMAL AHMED ,  NEUMAN GROVER HERBERT ,  SMITH TODD ALLEN

IPC: G06F12/00 ,  G06F12/08

Abstract: In a distributed environment several data processing systems are interconnected across a network system (3). A distributed services program installed on the systems in the network allows the processors to access data files (5) distributed across the various nodes (A,B) of the network without regard to the location of the data file in the network. The processing system accessing the file, referred to as the client processing system, utilizes a client cache (12B) within its operating system (11B) to store the data file. Utilizing the client cache minimizes the number of reads and writes that must go over the network (3) to the server processing system where the file physically resides. The system and method of this invention prevents a process in the client processing system from accessing data in the client cache that has been modified at another node (A) in the network. The blocks of data in the client cache (12B) are tested for validity in the client processing system by using modification times as measured by the server processing system. If the cache data blocks are determined to be valid, the data is accessed from the client cache. If the cache data blocks are determined to be invalid, the data blocks are discarded, and the file is accessed from the server processing system.

公开(公告)号：AU623446B2

公开(公告)日：1992-05-14

申请号：AU4452389

申请日：1989-11-09

Applicant: IBM

Inventor： CHANG ALBERT ,  ROGERS MARK DOUGLASS

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009

Abstract: Multiple external page table (XPT) structure geometries provide efficient organisation and management of paged, segmented virtual memory systems. First and second small XPT geometries are provided for file mapping of files of a predetermined size for code segments, and file mapping of files exceeding the predetermined size for process private segments, respectively. A large XPT geometry is for working storage segments containing shared library routines. A uniform addressing scheme accesses page state information for second small and large XPT geometries having root blocks. Selected XPT structure direct blocks are pre-allocated for large XPT structures for address ranges to be referenced to reduce page faults.

公开(公告)号：BR8700175A

公开(公告)日：1987-12-01

申请号：BR8700175

申请日：1987-01-16

Applicant: IBM

Inventor： CHANG ALBERT ,  MERGEN MARK FREDERICK ,  O'QUIN JOHN THOMAS II ,  O'QUIN JOHN CLAUDE III ,  ROGERS MARK DOUGLASS

IPC: G06F9/48 ,  G06F12/10 ,  G06F12/08 ,  G06F13/24

公开(公告)号：CA1200917A

公开(公告)日：1986-02-18

申请号：CA443872

申请日：1983-12-21

Applicant: IBM

Inventor： CHANG ALBERT ,  COCKE JOHN ,  MERGEN MARK F ,  RADIN GEORGE

IPC: G06F13/00 ,  G06F11/07 ,  G06F12/00 ,  G06F12/10 ,  G06F12/14 ,  G06F9/36

Abstract: VIRTUAL MEMORY ADDRESS TRANSLATION MECHANISM WITH CONTROLLED DATA PERSISTENCE Memory address translation and control system converts virtual memory addresses of a CPU into real memory addresses and for controlling memory functions. Address translation function comprises converting the virtual address into an effective address using a register set addressable by a small field of the CPU generated virtual address which converts the virtual address into an expanded form; and converting the effective address into a real memory address. The effective address is then used in the address translation step. To enhance the translation of frequently used virtual addresses, Translation Look-Aside Buffers (TLB) contain current effective to real address translations. The TLBs are addressed using a subset of the effective address. The contents of the addressed TLB is examined for a match with the effective address. When matched, successful address translation is possible and the real address stored in the TLB is available for system use. If not matched, the page frame tables stored in main memory are accessed for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.