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    2.
    发明专利
    未知

    公开(公告)号：DE3485929T2

    公开(公告)日：1993-04-01

    申请号：DE3485929

    申请日：1984-05-30

    Applicant: IBM

    Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  HAO HSIEH TUNG ,  MARKSTEIN PETER WILLY ,  RADIN GEORGE

    IPC: G06F9/30 ,  G06F7/493 ,  G06F7/50 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F9/46

    Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

    3.
    发明专利
    未知

    公开(公告)号：DE3481560D1

    公开(公告)日：1990-04-12

    申请号：DE3481560

    申请日：1984-05-30

    Applicant: IBM

    Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  HAO HSIEH TUNG ,  MARKSTEIN PETER WILLY ,  RADIN GEORGE

    IPC: G06F9/45 ,  G06F9/30 ,  G06F9/32 ,  G06F9/48 ,  G06F9/46

    Abstract: @ A mechanism for performing a run-time storage ad-dress validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry (52) for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.

    7.
    发明专利
    未知

    公开(公告)号：DE3485929D1

    公开(公告)日：1992-10-29

    申请号：DE3485929

    申请日：1984-05-30

    Applicant: IBM

    Inventor： AUSLANDER MARC ALAN ,  COCKE JOHN ,  HAO HSIEH TUNG ,  MARKSTEIN PETER WILLY ,  RADIN GEORGE

    IPC: G06F9/30 ,  G06F7/493 ,  G06F7/50 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32 ,  G06F9/46

    Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.

    9.
    发明专利
    未知

    公开(公告)号：DE3582974D1

    公开(公告)日：1991-07-04

    申请号：DE3582974

    申请日：1985-07-08

    Applicant: IBM

    Inventor： AUSLANDER MARC ALAN ,  HOPKINS MARTIN EDWARD ,  MARKSTEIN PETER WILLY

    IPC: G06F9/44 ,  G06F9/45

    Abstract: A method operable within an optimizing compiler generating Basis items and Kill Sets for use during subsequent global common subexpressions elimination and code motion procedures. More particularly, the method comprises assigning a symbolic register to each non-basis element to be computed as follows: creating a tuple (v) for each computation which is to be converted to a machine instruction by the compiler creating a table (optimally, a hash table) having an entry for all the tuples in the program being compiled; for every Basis element in a tuple being entered in the table a symbolic register uniquely assigned to that tuple is added to the Kill Set for that Basis element. For every non-basis element "n" in the tuple being entered into the table, the uniquely assigned symbolic register for that tuple is added to the Kill Sets for all the Basis elements in whose Kill Sets that non-basis element "n" appears. The symbolic register assigned to the tuple in the table is chosen to total the result of the computation of the non-basis element; and finally, a second table is constructed so that given a symbolic register, the computation which it represents can be retrieved.

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