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公开(公告)号：DE3382307D1
公开(公告)日：1991-07-11
申请号：DE3382307
申请日：1983-12-22
Applicant: IBM
Inventor： CHANG ALBERT , COCKE JOHN , MERGEN MARK , RADIN GEORGE
Abstract: A virtual memory address translation mechanism is provided for converting virtual memory addresses provided by a CPU into real memory addresses within page frames in a large hierachial memories wherein the real memory space is substantially smaller than the scope of the virtual memory. The conversion or translation mechanism includes a combined table in the memory which includes a first list covering the respective virtual address of each memory address (Inverted Page or IPT) and a second list connecting each of a plurality of hashed addresses with a predetermined initial virtual address of a linked group of virtual addresses, each of which when hashed produces the connected hashed address (Hashed Addressed Table, HAT). The system also has means for hashing a selected virtual address to produce a hashed address. Also included in apparatus for sequentially searching through the linked group of virtual addresses in the combined table until a selected virtual address is located as well as apparatus responsive to the location of a particular selected virtual address for accessing from the first list, the real memory address of the located virtual address.
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公开(公告)号：DE3485929D1
公开(公告)日：1992-10-29
申请号：DE3485929
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.
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公开(公告)号：CA1199414A
公开(公告)日：1986-01-14
申请号：CA440032
申请日：1983-10-20
Applicant: IBM
Inventor： FISK DALE E , GRIFFITH ROBERT L , HOMAN MERLE E , RADIN GEORGE , RICHARDS WALDO J
Abstract: If a predetermined field within a source instruction indexes and accesses a body of control information from memory, and if control information designates the field-to-field (register-to-register) mapping, then a skeleton target instruction can be filled in by either selectively copying the fieldsof the source instruction or otherwise computing same. If the mapping is executed by an interposed independent processor then overlapping of such conversion enhances throughput, the independent processor converting multifield instructions for a CPU of a first kind to multifield instructions for a CPU of a second kind without disrupting the logical flow or execution of either source or target instruction streams.
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公开(公告)号：AU574737B2
公开(公告)日：1988-07-14
申请号：AU3548884
申请日：1984-11-16
Applicant: IBM
Inventor： FISK DALE EDWARD , PERIERA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
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公开(公告)号：CA1200917A
公开(公告)日：1986-02-18
申请号：CA443872
申请日：1983-12-21
Applicant: IBM
Inventor： CHANG ALBERT , COCKE JOHN , MERGEN MARK F , RADIN GEORGE
Abstract: VIRTUAL MEMORY ADDRESS TRANSLATION MECHANISM WITH CONTROLLED DATA PERSISTENCE Memory address translation and control system converts virtual memory addresses of a CPU into real memory addresses and for controlling memory functions. Address translation function comprises converting the virtual address into an effective address using a register set addressable by a small field of the CPU generated virtual address which converts the virtual address into an expanded form; and converting the effective address into a real memory address. The effective address is then used in the address translation step. To enhance the translation of frequently used virtual addresses, Translation Look-Aside Buffers (TLB) contain current effective to real address translations. The TLBs are addressed using a subset of the effective address. The contents of the addressed TLB is examined for a match with the effective address. When matched, successful address translation is possible and the real address stored in the TLB is available for system use. If not matched, the page frame tables stored in main memory are accessed for the desired effective address and if found the associated real address is accessed. Further a special data field is provided in both the TLBs and the page frame tables in main memory wherein a bit is provided for each line in the referenced page at a given effective to real address translation which bits may be used to indicate when a line of data has been accessed or altered.
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Patent Agency Ranking
公开(公告)号：BR8406533A
公开(公告)日：1985-10-15
申请号：BR8406533
申请日：1984-12-18
Applicant: IBM
Inventor： FISK DALE EDWARD , PEREIRA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
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公开(公告)号：DE3485929T2
公开(公告)日：1993-04-01
申请号：DE3485929
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism including an expanded condition register for use in a reduced instruction set computing system which facilitates the performance of single machine cycle instructions on the system and further provides for the efficient execution of more complex instructions which are not susceptible of being completed in a single machine cycle. More particularly, a mechanism is provided for setting the bits of the expanded condition register whereby a more efficient restart is possible after a machine interrupt and whereby the results of intermediate operations of certain multistep logic and arithmetic operations are maintained in the condition register in order that the cycle time of such multistep operations may be kept to a minimum, and when necessary, may be executed with greater efficiency. Still more particularly, the condition register architecture provides for the efficient handling of multiply and divide operations and provides for the more efficient execution of certain decimal operations within such a reduced instruction set host computer system.
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公开(公告)号：DE3481560D1
公开(公告)日：1990-04-12
申请号：DE3481560
申请日：1984-05-30
Applicant: IBM
Inventor： AUSLANDER MARC ALAN , COCKE JOHN , HAO HSIEH TUNG , MARKSTEIN PETER WILLY , RADIN GEORGE
Abstract: @ A mechanism for performing a run-time storage ad-dress validity check within one machine cycle. The mechanism, functioning together with an intelligent compiler, eliminates the need for hardware implementation of a storage validity check. More particularly, the mechanism performs its function in one machine cycle in the event that a trap exception does not cause an interrupt. In the rare instance when an interrupt is necessary, a number of machine cycles will be impacted. The mechanism comprises a minimum amount of logic circuitry (52) for determining the trap condition operating in conjunction with conventional, previously existing compare, branch instruction testing, and interrupt generation circuitry.
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公开(公告)号：AU3548884A
公开(公告)日：1985-07-04
申请号：AU3548884
申请日：1984-11-16
Applicant: IBM
Inventor： FISK DALE EDWARD , PERIERA LAWRENCE WILLIAM , RADIN GEORGE
Abstract: An internal bus mechanism for implementation in a computing system characterized by having a limited number of primitive general function instructions provided for controlling all system operations. The architecture oftheinternal bus mechanism defines a bus instruction format which specifies the bus unit being requested, the operation being requested, and sufficient data to specify the operands necessary to perform the requested operations. Two basic classes of instructions are provided, one wherein the CPU waits until a requested operation is performed and the other wherein the CPU issues an instruction to a bus unit and proceeds to execute further instructions in parallel with the operation of the bus unit. If desired, various units of the memory hierarchy may be designated and operated as bus units. To further the philosophy of a primitive instruction set, the present architecture utilizes a small number of bus unit instructions to replace a large number of additional system instructions which would be necessary if the bus units were arch itected as part of the CPU itself. Hardware design and system protocols are disclosed and described for implementing these architectural objectives.
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10.发明专利
公开(公告)号：HK7695A
公开(公告)日：1995-01-27
申请号：HK7695
申请日：1995-01-19
Applicant: IBM
Inventor： CARRUBBA FRANK PAUL , COCKE JOHN , KREITZER NORMAN , RADIN GEORGE
Abstract: A hierarchical memory system for use with a high speed data processor characterized by having separate dedicated cache memories for storing data and instructions and further characterized by each cache having a unique cache directory containing a plurality of control bits for assisting line replacement with the individual cache memories and for eliminating many accesses to main memory and to insure that unnecessary or incorrect data is never stored back into said main memory. … The present cache architecture and control features render broadcasting between the data cache and instruction cache unnecessary. Moditication of the instruction cache is not permitted. Accordingly, control bits indicating a modification in the cache directory for the instruction cache are not necessary and similarly it is never necessary to store instruction cache lines back into main memory since their modification is not permitted. … The cache architecture and controls permit normal instruction and data cache fetches and data cache stores. Additionally, special instructions are provided for setting the special control bits provided in both the instruction and data cache directories, independently of actual memory accessing OPS by the CPU and for storing and loading cache lines independently of memory OPS by the CPU.
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