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    12.
    发明专利
    未知

    公开(公告)号：DE2258383A1

    公开(公告)日：1973-06-28

    申请号：DE2258383

    申请日：1972-11-29

    Applicant: IBM

    Inventor： CROISIER ALAIN

    IPC: G08C19/12 ,  G01R25/00 ,  G08C19/22 ,  H03D3/00 ,  H04L27/233

    Abstract: A detector in which the phase theta of an applied sinusoid S = R Sin theta is digitally obtained by determining the unit circle equivalent of the quadrant of the phase angle from the sign match or mismatch between the sinusoid S and its quadrature S = R Cos theta and by determining the unit circle equivalent of an acute reference angle alpha derived according to the relation alpha = tan 1 eln S ln S . The signal and its quadrature are periodically sampled and digitally sign and magnitude encoded. The digital magnitudes ¦S¦ and ¦S¦ are applied to table look-up devices to obtain ln¦S¦ and ln¦S¦ respectively. A digital subtractor forms ln¦S¦ - ln¦S¦, which difference is then applied to a table look-up device to obtain alpha . A logic element responsive to the encoded signs and the derived reference angle alpha generates the coded equivalent to theta .

    DATA TRANSMISSION SYSTEM
    14.
    发明专利
    DATA TRANSMISSION SYSTEM 未知

    公开(公告)号：GB1221964A

    公开(公告)日：1971-02-10

    申请号：GB1623368

    申请日：1968-04-04

    Applicant: IBM

    Inventor： CROISIER ALAIN ,  FALCOZ ALAIN

    IPC: G06F13/42 ,  H04L12/40

    Abstract: 1,221,964. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 4 April, 1968 [18 April, 1967], No. 16233/68. Heading H4P. [Also in Division G4] A data transmission system (Fig. 1) comprises transmission and reception units 1, 2 which may be components of a data processing unit or of magnetic tape stores, printers, displays or punches. These are unidirectionally coupled at 14 to a channel comprising a data line 7, a clock line 8, and a transmission demand line 9. Line 7 may be plural to transmit a byte of data in parallel. Units 1, 2 have associated control units 5, 6 connected over lines 10, 11, 39 and 12, 13, 40 driving transmitters 31, 32; 33, 34 and receiving the outputs of receivers 41, 42; 44, 45, and are directly coupled to line 7 over receivers 43, 46. Thus unit 1 is coupled to line 7 over transmitter 31 and receiver 43; to line 8 over receiver 42, and to line 9 over transmitter 32 and receiver 41. Control unit 5 (Fig. 2), to which control unit 6 is similar, comprises a transmission demand trigger 22 and a data trigger 48 receiving "1" inputs over lines 11, 10 from unit 1. The "1" output 27 of trigger 22 when energized in response to the "1" input is connected to AND units 16, 23; the former also receiving operating signals from receiver 42 coupled to clock line 8, from inverter 18 driven from receiver 41 coupled to demand line 9, and from delay 20 coupled to the output of AND unit 23, which receives signals from trigger 22, and over delay 24 from receiver 42; to energize transmitter 32 coupled to demand line 9. Trigger 48 energizes AND unit 28 together with signals from the output of AND unit 16, and this output also energizes the "O" inputs of triggers 22, 48 over delay 35, while the AND unit 28 operates transmitter 31 coupled to data line 7. In operation, for unit 1 to transmit a binary digit, trigger 48 is set to "1" state to energize AND unit 28 and trigger 22 is also set to "1" to operate trigger 22 and energize AND gate 16. The next succeeding clock pulse over receiver 42 energizes AND unit 16 and also AND unit 23 after delay in 24, so as to energize transmitter 32 which imposes a transmission demand signal on line 9, and energizes the AND unit 16 after delay in 20. Inverter 18 driven from receiver 41 coupled to the transmission demand signal on line 9 energizes AND unit 16, in the absence of a transmission demand signal on line 9 and presence of a clock pulse on line 8, to actuate AND circuit 28 and transmitter 31 to transmit the "1" bit stored at 48 into line 7. After delay at 35, trigger circuits 22, 48 are reset with unit 1; indicating that data has been transmitted. If the AND unit 16 is inactivated for want of one or more inputs, triggers 22, 48 are not operated and the data signal is held stored in unit 5 until a clock pulse occurs in line 8 without a demand signal on line 9. As shown, units 1, 2 are coupled to the transmission channel so that signals are transmitted to the right and received from the left, and a transmission demand signal disables all other units from transmissions. Each TR unit may have dual control units 5 for rightward and leftward transmission; lines 7, 9 being doubled to avoid interference.

    15.
    发明专利
    未知

    公开(公告)号：DE1943185A1

    公开(公告)日：1970-03-12

    申请号：DE1943185

    申请日：1969-08-25

    Applicant: IBM

    Inventor： CROISIER ALAIN ,  NUSSBAUMER HENRI-JEAN

    IPC: H04M11/06 ,  H04L25/48 ,  H04L25/497 ,  H04M11/00

    Abstract: 1,271,753. Digital transmission systems. INTERNATIONAL BUSINESS MACHINES CORP. 15 Aug., 1969 [4 Sept., 1968], No. 40926/69. Addition to 1,154,648. Heading H4P. In a digital transmission system each digital pulse, of duration T, is represented by a pulse sequence comprising a main pulse with two " echo " pulses following and preceding it. Successive sequences overlap, and the system is so designed that the resulting sequence is a signal (Sin (#t/2D).Cos 2#ft)/t, where T=pD (p is integral), and f=(2n-1)/4D. At the receiver this signal is demodulated with a frequency f+1/4D, the demodulated signal being sampled at a rate 1/T. The main pulses may be multi-level signals. In an example in which n = 2 and p = 1, binary data is passed to a 3-bit shift register stepped at bit rate. The parallel output of the register is selectively passed via gates, enabled by three bit-rate time-staggered clock trains, to a circuit which weights its inputs and presents a signal which, after low-pass filtering, has the waveform defined above.

    Switching networks
    19.
    发明专利
    Switching networks 未知

    公开(公告)号：GB1110367A

    公开(公告)日：1968-04-18

    申请号：GB1271366

    申请日：1966-03-23

    Applicant: IBM

    Inventor： CROISIER ALAIN

    IPC: H04Q3/54

    Abstract: 1,110,367. Automatic exchange systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. 23 March, 1966 [2 April, 1965], No. 12713/66. Heading H4K. A switching network comprises a number of closed meshes defined by conductors arranged in a co-ordinate manner, the intersecting points or nodes being provided with switches for connecting together any pair of conductors. In a 2 co-ordinate network, Fig. 1, subscribers' lines are connected to the nodes N over switches A, and each node may be connected to any one of 4 adjacent nodes over switches X, Y, the object being to interconnect pairs of subscribers over the shortest available path with a low blocking factor in relation to the switching equipment employed. The blocking factor may be further reduced if provision is made for rearranging existing connections. Thus, for example, with the 4 existing connections shown in Fig. 3a, if a connection is required between B33 and B43 it can be obtained by changing the B32, B44 connection to that shown dotted in Fig. 3d. The average path length of a connection may be reduced by allotting a subscriber's line to more than one node. In Fig. 7 (not shown) auxiliary cross-point matrices are employed for connecting any one of 2 (or 4) lines to any one of 2 (or 4) nodes. The arrangement may be extended to more than 2 co-ordinates, and it is found that for a given number of nodes an optimum result is obtained by suitable choice of the number of co-ordinates. The switches at the nodes may be of multi-position mechanical type, cross-bars or reed relays. The switches are conveniently controlled by a central processing unit CPU, Fig. 13, which obtains the addresses of the calling and called subscribers from a line scanner 102 and sends signals indicative of the shortest available path to a switch controller 105. If the CPU fails the memory of the network may be recaptured by the use of a network scanner 106.

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