BUS INTERFACE DEVICE FOR A DATA PROCESSING SYSTEM

    公开(公告)号:DE3375611D1

    公开(公告)日:1988-03-10

    申请号:DE3375611

    申请日:1983-03-29

    Applicant: IBM IBM FRANCE

    Abstract: A number (e.g. sixteen) of processors are connected to a central control unit by a common bus having half that number of wires (D0-D7) reserved for a byte of data or control bits, one line for a parity bit and one for a control bit. In the bus interface each line (D0-D7) is associated with two flip-flops (40,41) having direct and inverted (44) inputs of a first clock signal (CLK1). When received bits are in NRZ code with duration equal to half the clock period, output OR gates (47) reproduce resynchronised input bits. Processors divided into two equal gps. request access during one or other phase of a second clock signal. The state of access requests is indicated by memory flip-flops (48,49) when the bus is free.

    3.
    发明专利
    未知

    公开(公告)号:FR2414830A1

    公开(公告)日:1979-08-10

    申请号:FR7836583

    申请日:1978-12-20

    Applicant: IBM

    Abstract: This specification describes a charge-transfer device transversal filter chip in which an input signal is fed in parallel into a number of channels the outputs of which are summed together to provide the desired transversal filter transfer function. Each channel contains an analog shift register, a signal splitter and a polarity selector. The shift registers are of unequal length to provide a different delay thru each channel. The signal splitter provides a plurality of signal paths thru each channel while the polarity selector determines whether a given path in a given channel is added or subtracted in the summation to determine the gain of the given channel in the summation.

Patent Agency Ranking